diff options
| author | Simon Glass <sjg@chromium.org> | 2014-11-24 21:18:18 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-11-25 06:34:14 -0700 |
| commit | 24774278c9dc4e44487cb565282d4a4830327fd4 (patch) | |
| tree | 89880053b7c4baa1f78ec892a4eff9551cddcb8d /arch/x86/include | |
| parent | d1ef1132bbcf2cc14f36f5114d88ff3fa74106df (diff) | |
| download | u-boot-24774278c9dc4e44487cb565282d4a4830327fd4.zip u-boot-24774278c9dc4e44487cb565282d4a4830327fd4.tar.gz u-boot-24774278c9dc4e44487cb565282d4a4830327fd4.tar.bz2 | |
x86: ivybridge: Add northbridge init functions
Add init for the northbridge, another part of the platform controller hub.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/model_206ax.h | 4 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-ivybridge/sandybridge.h | 13 |
2 files changed, 16 insertions, 1 deletions
diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h index 8281d7a..7b4f2e7 100644 --- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h +++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h @@ -79,4 +79,8 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); +int cpu_config_tdp_levels(void); + #endif diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index 114ee19..cf7457f 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -97,11 +97,22 @@ /* * MCHBAR */ -#define MCHBAR_REG(reg) (DEFAULT_RCBA + (reg)) +#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg)) #define SSKPD 0x5d14 /* 16bit (scratchpad) */ #define BIOS_RESET_CPL 0x5da8 /* 8bit */ +/* + * DMIBAR + */ + +#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x) + +int bridge_silicon_revision(void); + +void northbridge_enable(pci_dev_t dev); +void northbridge_init(pci_dev_t dev); + void report_platform_info(void); void sandybridge_early_init(int chipset_type); |