rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-04-08	riscv: add support for multi-hart systems	Lukas Auer	5	-2/+147
2019-04-08	riscv: save hart ID in register tp instead of s0	Lukas Auer	1	-2/+2
2019-04-08	riscv: delay initialization of caches and debug UART	Lukas Auer	1	-8/+8
2019-04-08	riscv: implement IPI platform functions using SBI	Lukas Auer	3	-0/+31
2019-04-08	riscv: import the supervisor binary interface header file	Lukas Auer	1	-0/+94
2019-04-08	riscv: add infrastructure for calling functions on other harts	Lukas Auer	5	-0/+197
2019-02-27	riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd	Anup Patel	1	-0/+1
2019-02-27	riscv: Add SiFive FU540 board support	Anup Patel	1	-0/+4
2019-02-27	riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems	Anup Patel	1	-0/+20
2019-02-27	riscv: Add place-holder asm/arch/clk.h for driver compilation	Anup Patel	1	-0/+14
2019-02-27	riscv: Add asm/dma-mapping.h for DMA mappings	Anup Patel	1	-0/+38
2019-02-27	riscv: Rename cpu/qemu to cpu/generic	Anup Patel	5	-2/+2
2019-01-15	riscv: qemu: define standalone load address	Lukas Auer	1	-1/+1
2019-01-15	riscv: remove RISC-V standalone linker script	Lukas Auer	1	-1/+0
2019-01-15	riscv: use invalidate/flush_*cache_range functions in cache.c	Lukas Auer	1	-2/+2
2019-01-15	riscv: move the AX25-specific implementation of flush_dcache_all	Lukas Auer	2	-6/+26
2019-01-15	riscv: clarify error message on undefined exceptions	Lukas Auer	1	-1/+2
2018-12-31	riscv: bootm: Support booting VxWorks	Bin Meng	1	-1/+7
2018-12-18	riscv: Remove ae350.dts	Bin Meng	1	-229/+0
2018-12-18	riscv: bootm: Change to use boot_hart from global data	Bin Meng	1	-1/+1
2018-12-18	riscv: Save boot hart id to the global data	Bin Meng	3	-0/+24
2018-12-18	riscv: Adjust the _exit_trap() position to come before handle_trap()	Bin Meng	1	-32/+30
2018-12-18	riscv: Return to previous privilege level after trap handling	Bin Meng	1	-8/+0
2018-12-18	riscv: Fix context restore before returning from trap handler	Bin Meng	1	-1/+1
2018-12-18	riscv: Move trap handler codes to mtrap.S	Bin Meng	3	-90/+112
2018-12-18	riscv: Do some basic architecture level cpu initialization	Bin Meng	1	-1/+26
2018-12-18	riscv: Add indirect stringification to csr_xxx ops	Bin Meng	1	-7/+9
2018-12-18	riscv: Update supports_extension() to use desc from cpu driver	Bin Meng	1	-0/+26
2018-12-18	riscv: Add exception codes for xcause register	Bin Meng	1	-0/+15
2018-12-18	riscv: Add CSR numbers	Bin Meng	1	-0/+221
2018-12-18	riscv: Remove non-DM version of print_cpuinfo()	Bin Meng	1	-37/+0
2018-12-18	riscv: Probe cpus during boot	Bin Meng	2	-0/+27
2018-12-18	riscv: Enlarge the default SYS_MALLOC_F_LEN	Bin Meng	1	-0/+3
2018-12-18	riscv: qemu: Add platform-specific Kconfig options	Bin Meng	2	-0/+12
2018-12-18	riscv: Implement riscv_get_time() API using rdtime instruction	Anup Patel	3	-0/+47
2018-12-18	riscv: Add a SYSCON driver for SiFive's Core Local Interruptor	Bin Meng	5	-0/+116
2018-12-18	riscv: Introduce a Kconfig option for machine mode	Anup Patel	1	-5/+16
2018-12-18	riscv: ax25: Hide the ax25-specific Kconfig option	Bin Meng	2	-11/+18
2018-12-18	riscv: qemu: Create a simple-bus driver for the soc node	Bin Meng	1	-0/+14
2018-12-18	riscv: add Kconfig entries for the code model	Lukas Auer	2	-1/+26
2018-12-05	riscv: ax25-ae350: Pass dtb address to u-boot with a1 register	Rick Chen	1	-2/+0
2018-12-05	riscv: Add kconfig option to run U-Boot in S-mode	Anup Patel	4	-17/+48
2018-12-02	riscv: efi: Generate Microsoft PE format compliant images	Bin Meng	1	-6/+6
2018-11-26	riscv: cache: Implement i/dcache [status, enable, disable]	Rick Chen	9	-10/+146
2018-11-26	riscv: dts: Add ae350_32.dts for RV32I	Rick Chen	3	-1/+458
2018-11-26	riscv: dts: Sync to Linux Kernel ae350 dts.	Rick Chen	1	-15/+92
2018-11-26	riscv: align bootm implementation with that of other architectures	Lukas Auer	1	-27/+70
2018-11-26	riscv: save hart ID and device tree passed by prior boot stage	Lukas Auer	2	-2/+16
2018-11-26	riscv: do not blindly modify the mstatus CSR	Lukas Auer	1	-4/+4
2018-11-26	riscv: remove unused labels in start.S	Lukas Auer	1	-9/+0