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2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"WIP/20May2024-nextTom Rini1-1/+0
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini1-0/+1
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-06arm: imx: Remove <common.h> and add needed includesTom Rini1-1/+0
Remove <common.h> from all mach-imx, CPU specific sub-directories and include/asm/arch-mx* files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-18Merge tag 'v2024.01-rc5' into nextTom Rini1-0/+1
Prepare v2024.01-rc5
2023-12-14ddr: imx: Add 3600 MTps rate supportMarek Vasut1-0/+1
Add PLL settings for DDR 3600 MTps . This is very similar to 3200 MTps PLL setting, except the divider is not 9 but 8 . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13clock_imx8mm: Add a stub for imx8mp_fec_interface_init()Fabio Estevam1-0/+7
When CONFIG_DWC_ETH_QOS_IMX=y and CONFIG_FEC_MXC is not selected, the following warning is seen: arch/arm/mach-imx/imx8m/clock_imx8mm.c: In function 'board_interface_eth_init': arch/arm/mach-imx/imx8m/clock_imx8mm.c:914:24: warning: implicit declaration of function 'imx8mp_fec_interface_init; did you mean 'imx8mp_eqos_interface_init'? [-Wimplicit-function-declaration] Fix it by adding a stub for imx8mp_fec_interface_init() to handle this case. This follows the same approach done on imx8mp_eqos_interface_init(). Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2023-07-13imx: imx8m: clock: not configure reserved SRC registerPeng Fan1-1/+0
i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-30arm64: imx8mm: imx8mn: imx8mp: Drop FEC GPR[1] board workaroundMarek Vasut1-47/+0
The FEC interface mode is now configured in common board_interface_eth_init() and called by FEC MAC driver when appropriate. Drop the board side duplicates if the same functionality. Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30arm64: imx8mp: Drop EQoS GPR[1] board workaroundMarek Vasut1-47/+0
The EQoS interface mode is now configured in common board_interface_eth_init() and called by EQoS MAC driver when appropriate. Drop the board side duplicates if the same functionality. Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30ARM: imx: imx8mp: fix enable_i2c_clkRasmus Villemoes1-2/+2
In order for i2c_num==4 and 5 to stay invalid for non-imx8mp SOCs, the i2c_ccgr[] array must be sized by the number of initializers present, not with a hard-coded 6 which would implicitly initialize the last two elements with zeroes. Also, the bounds check is off-by-one. Fixes: c92c3a4453b8 "ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP" Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-03-30net: fec_mxc: Add board_interface_eth_init() for i.MX8M Mini/Nano/PlusMarek Vasut1-0/+46
Implement common board_interface_eth_init() and call it from the FEC driver to configure IOMUXC GPR[1] register according to the PHY mode obtained from DT. This supports all three interface modes supported by the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side configuration of the same IOMUX GPR[1] duplicated in the board files. Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M PlusMarek Vasut1-1/+58
Implement common board_interface_eth_init() and call it from the DWMAC driver to configure IOMUXC GPR[1] register according to the PHY mode obtained from DT. This supports all three interface modes supported by the i.MX8M Plus DWMAC and supersedes current board-side configuration of the same IOMUX GPR[1] duplicated in the board files. Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30net: dwc_eth_qos: Add DM CLK support for i.MX8M PlusMarek Vasut1-41/+0
The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc architecture code. Replace that with DM clock instead. This way, the driver claims all its required clock, enables and disables them, and even gets the CSR clock rate and sets the TX clock rate, without any need of architecture specific register fiddling. Drop the architecture specific code while at it too. The adjustment here is modeled after STM32MP15xx clock handling in this driver. Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-07ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MPMartyn Welch1-3/+9
The i.MX8MP SoC contains 2 more i2c buses. Add support for the configuration of these buses. Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-04-12ARM: imx: imx8m: Add 933 MHz PLL settingsMarek Vasut1-0/+1
Add settings for operating PLL at 933 MHz. This setting is useful in case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-02-05ARM: imx: imx8m: Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz optionsMarek Vasut1-0/+20
Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options for iMX8M SoCs in case they should be operated faster, e.g. to improve boot time. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2022-02-05ARM: imx: imx8m: Align PLL 1.2 GHz option with LinuxMarek Vasut1-3/+3
Linux uses slightly different divider settings for the 1.2 GHz PLL configuration, adjust the coefficients to match Linux. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2021-06-09arm: imx: imx8mm: correct unrecognized fracpll frequencyAndrey Zhizhikin1-1/+1
Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ() macro, which expands the value provided to the Hz range without taking into account the precise Hz setting. This causes the frequency of 266 MHz not ot be found in the imx8mm_fracpll_tbl, since it is entered there with a precise Hz value. This in turn causes the boot hang in SPL, as proper DDR fracpll frequency cannot be determined. Correct the value in imx8mm_fracpll_tbl to match the one expanded by MHZ(266) macro, rounding it down to MHz range only. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ye Li <ye.li@nxp.com> Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m") Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-06-09arm: imx: imx8mm: clock: make debug output more descriptiveAndrey Zhizhikin1-3/+3
Clock initialization functionality has ambitious debug messages, which are printed out when failures are triggered during execution: - Separate frequency table lookup functions have the the same output that makes it impossible to understand which function failed and produced the output - PLL decoding routine has a generic debug statement printed, which does not state the actual value failed to be found Extend the output for both cases with prefixing table lookup functions output with function name, and report the failed value in PLL decoding routine. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-05-24ARM: imx8m: fix imx_eqos_txclk_set_rate() type mismatch for LTOMarek Behún1-1/+1
When building imx8mp_evk_defconfig with LTO, the compiler complains about type mismatch of function imx_eqos_txclk_set_rate() in file drivers/net/dwc_eth_qos.c:845:12 which contains a weak definition of this function, vs file arch/arm/mach-imx/imx8m/clock_imx8mm.c which contains an implementation. Change the type of this function in the implementation to fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-04-08iMX8M: Add support to enable CONFIG_IMX_HABYe Li1-0/+8
Add some SOC level codes and build configurations to use HAB lib for CONFIG_IMX_HAB (secure boot), like adding the SEC_CONFIG fuse, enable fuse driver, CAAM clock function, and add CAAM secure RAM to MMU table. The FSL_CAAM is temporally not enabled for iMX8M when CONFIG_IMX_HAB is set, because we don't need the CAAM driver for SPL. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass1-0/+1
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-17imx8m: clock_imx8mm: add missed returnPeng Fan1-0/+1
Add missed return Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14imx8m: add eqos clkPeng Fan1-0/+90
Add imx_eqos_txclk_set_rate/imx_get_eqos_csr_clk to override the weak function in driver Add set_clk_eqos to configure eQoS clk Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14imx8m: add sdhc/nand/ecspi clk apiPeng Fan1-0/+66
Current DM CLK is a bit complicated, for simplity, let DM clk only support enable/disable/get_rate. For the expected rate settings, we use non-DM clk to do that. Then we could have simple DM clk for i.MX and could also share between SPL/U-Boot proper. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14imx8m: configure NoC clkPeng Fan1-0/+13
Configure NoC clk for better system performance Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14imx8m: configure arm clk sources from PLLPeng Fan1-1/+129
A53 CCM root max support 1GHz, to support high freq, we need to switch ARM clk sources from ARM PLL directly. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-01imx8mm: clock: fix fracpll decode issueYe Li1-12/+12
The fracpll decoding is using the bit definitions for int pll. Most of them are same, but the CLKE bit is different. Fix the wrong CLKE_MASK for fracpll and correct all bit definitions in fracpll decoding. Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01ARM: imx: imx8mm: Add missing clock entries for FEC clockMarek Vasut1-0/+49
All the FEC ethernet clock entries for iMX8MM are missing, while they are already present on iMX8MQ. Fill in the nodes on iMX8MM, as the FEC ethernet gets bogus clock information otherwise which makes ethernet inoperable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-01-20imx8m: clock_imx8mm: Staticize functionsAlifer Moraes1-5/+5
Functions fracpll_configure(), decode_intpll(), decode_fracpll(), get_root_src_clk() and get_root_clk() are used only in the scope of this file, so make them static to fix the following sparse warnings: arch/arm/mach-imx/imx8m/clock_imx8mm.c:50:5: warning: no previous prototype for ‘fracpll_configure’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:271:5: warning: no previous prototype for ‘decode_intpll’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:418:5: warning: no previous prototype for ‘decode_fracpll’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:483:5: warning: no previous prototype for ‘get_root_src_clk’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:527:5: warning: no previous prototype for ‘get_root_clk’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
2020-01-08imx: imx8m: only support non-dm code in clock_imx8mm.cPeng Fan1-33/+306
The drivers/clk/imx/*.c are used for CLK dm case, the clock_imx8mm.c is used for non CLK dm case, let's split it. Sometimes it is hard to enable CLK dm in SPL stage, considering code size, malloc size requirement, the splittion will make it easy to use non CLK dm in SPL stage. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: imx8m: add 1GHz fracpll entryPeng Fan1-0/+1
4000MTS DDR needs 1GHz fracpll, so add the entry Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: add clk support for i.MX8MMPeng Fan1-0/+306
Introduce clk implementation for i.MX8MM, including pll configuration, ccm configuration. Mostly will be done clk dm driver, but such as DRAM part, we still use non clk dm driver, because we have limited sram. Signed-off-by: Peng Fan <peng.fan@nxp.com>
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