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| author | Marek Vasut <marex@denx.de> | 2023-03-06 15:53:51 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2023-03-30 13:47:04 +0200 |
| commit | 4bdc3524d76eb9bc6e30b74f3dfe4a0ae5e5b1b6 (patch) | |
| tree | 4726fa1c5d051817d3ad833e284d2e8c76e191f5 /arch/arm/mach-imx/imx8m/clock_imx8mm.c | |
| parent | 80a34e4008f022a78409657d2b0a5020a472db2e (diff) | |
| download | u-boot-4bdc3524d76eb9bc6e30b74f3dfe4a0ae5e5b1b6.zip u-boot-4bdc3524d76eb9bc6e30b74f3dfe4a0ae5e5b1b6.tar.gz u-boot-4bdc3524d76eb9bc6e30b74f3dfe4a0ae5e5b1b6.tar.bz2 | |
net: fec_mxc: Add board_interface_eth_init() for i.MX8M Mini/Nano/Plus
Implement common board_interface_eth_init() and call it from the FEC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side
configuration of the same IOMUX GPR[1] duplicated in the board files.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/arm/mach-imx/imx8m/clock_imx8mm.c')
| -rw-r--r-- | arch/arm/mach-imx/imx8m/clock_imx8mm.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 1546c9b..32f8623 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -968,10 +968,56 @@ int set_clk_enet(enum enet_freq type) return 0; } + +static int imx8mp_fec_interface_init(struct udevice *dev, + phy_interface_t interface_type, + bool mx8mp) +{ + /* i.MX8MP has extra RGMII_EN bit in IOMUXC GPR1 register */ + const u32 rgmii_en = mx8mp ? IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN : 0; + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + clrbits_le32(&gpr->gpr[1], + rgmii_en | + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL); + + switch (interface_type) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RMII: + setbits_le32(&gpr->gpr[1], IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + setbits_le32(&gpr->gpr[1], rgmii_en); + break; + default: + return -EINVAL; + } + + return 0; +} #endif int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type) { + if (IS_ENABLED(CONFIG_IMX8MM) && + IS_ENABLED(CONFIG_FEC_MXC) && + device_is_compatible(dev, "fsl,imx8mm-fec")) + return imx8mp_fec_interface_init(dev, interface_type, false); + + if (IS_ENABLED(CONFIG_IMX8MN) && + IS_ENABLED(CONFIG_FEC_MXC) && + device_is_compatible(dev, "fsl,imx8mn-fec")) + return imx8mp_fec_interface_init(dev, interface_type, false); + + if (IS_ENABLED(CONFIG_IMX8MP) && + IS_ENABLED(CONFIG_FEC_MXC) && + device_is_compatible(dev, "fsl,imx8mp-fec")) + return imx8mp_fec_interface_init(dev, interface_type, true); + if (IS_ENABLED(CONFIG_IMX8MP) && IS_ENABLED(CONFIG_DWC_ETH_QOS) && device_is_compatible(dev, "nxp,imx8mp-dwmac-eqos")) |