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2023-08-17arm: Use builtins for ffs/flsSean Anderson1-1/+26
Since ARMv5, the clz instruction allows for efficient implementation of ffs/fls with builtins. Until ARMv7 (with Thumb-2), this instruction is only available in ARM mode. LTO makes it difficult to force specific functions to be in ARM mode, as it is effectively a form of very aggressive inlining. To work around this, fls/ffs are implemented in assembly for ARMv5 and ARMv6 when compiling U-Boot in Thumb mode. Overall, this saves around 75 bytes per call. This code is synced with v5.15 of the Linux kernel. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-08-09treewide: rework linker symbol declarations in sections headerShiji Yang1-3/+0
1. Convert all linker symbols to char[] type so that we can get the corresponding address by calling array name 'var' or its address '&var'. In this way, we can avoid some potential issues[1]. 2. Remove unused symbol '_TEXT_BASE'. It has been abandoned and has not been referenced by any source code. 3. Move '__data_end' to the arch x86's own sections header as it's only used by x86 arch. 4. Remove some duplicate declared linker symbols. Now we use the standard header file to declare them. [1] This patch fixes the boot failure on MIPS target. Error log: SPL: Image overlaps SPL Fixes: 1b8a1be1a1f1 ("spl: spl_legacy: Fix spl_end address") Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-07-21Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiWIP/21Jul2023Tom Rini1-5/+7
For once this adds USB support for two SoCs: the H616 and the F1C100s series. The rest is support for LPDDR3 DRAM chips on H616 boards. Gitlab CI passed, and I booted that briefly on an H616 and an F1C200s board. I don't have an H616 board with LPDDR3 DRAM, but reportedly that works for Mikhail, and doesn't regress on my DDR3 boards.
2023-07-21sunxi: H616: dram: split struct dram_paraAndre Przywara1-4/+6
Currently there is one DRAM parameter struct for the Allwinner H616 DRAM "driver". It contains many fields that are compile time constants (set by Kconfig variables), though there are also some fields that are probed and changed over the runtime of the DRAM initialisation. Because of this mixture, the compiler cannot properly optimise the code for size, as it does not consider constant propagation in its full potential. Help the compiler out by splitting that structure into two: one that only contains values known at compile time, and another one where the values will actually change. The former can then be declared "const", which will let the compiler fold its values directly into the code using it. We also add "const" tags for some new "struct dram_config" pointers, to further increase code optimisation. To help the compiler optimise the code further, the definition of the now "const struct dram_para" has to happen at a file-global level, so move that part out of sunxi_dram_init(). That results in quite some code savings (almost 2KB), and helps to keep the code small with the LPDDR3 support added later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21sunxi: H616: dram: const-ify DRAM function parametersAndre Przywara1-1/+1
There are quite some functions in the Allwinner H616 DRAM "driver", some of them actually change the parameters in the structure passed to them, but many are actually not. To increase the optimisation potential for the code, mark those functions that just read members of the passed dram_para struct as "const". This in itself does not decrease the code size, but lays the groundwork for future changes doing so. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-20arm: mx5: Correct mxc_set_clock function prototypeTom Rini1-1/+1
With gcc-13.1 we get a warning about enum vs int here, so correct the declaration to match the implementation. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-14arch: arm: npcm8xx: add cpu version and 4G ram supportJim Liu1-0/+1
Add npcm8xx A2 cpu version check and add 4G RAM support Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-13imx: imx8m: add CAAM_BASE_ADDRPeng Fan1-0/+1
Add CAAM_BASE_ADDR which will be used by priblob.c Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: ahab: Update AHAB for iMX8 and iMX8ULPYe Li1-0/+15
Abstract common interfaces for AHAB authentication operations. Then share some common codes for AHAB and SPL container authentication Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: imx8: bootaux: Add i.MX8 M4 boot supportYe Li1-0/+1
1. Implement bootaux for the M4 boot on i.MX8QM and QXP. Users need to download M4 image to any DDR address first. Then use the "bootaux <M4 download DDR address> [M4 core id]" to boot CM4_0 or CM4_1, the default core id is 0 for CM4_0. Since current M4 only supports running in TCM. The bootaux will copy the M4 image from DDR to its TCML. 2. Implment bootaux for HIFI on QXP command: bootaux 0x81000000 1 Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: bootaux: change names of MACROs used to boot MCU on iMX devicesPeng Fan3-3/+3
The current bootaux supports i.MX8M and i.MX93, but the name "_M4_" implies that the SoCs have Cortex-M4. Actually i.MX8MM/Q use Cortex-M4, i.MX8MN/P use Cortex-M7, i.MX93 use Cortex-M33, so use "_MCU_" in place of "_M4_" to simplify the naming. Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: imx8ulp: start the ELE RNG at bootPeng Fan1-0/+1
On the imx8ulp A1 SoC, the ELE RNG needs to be manually started. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: ele_api: add DEK Blob generationPeng Fan1-1/+1
- Add crc computation. - Add ele_generate_dek_blob API for encrypted boot support. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: ele_api: support program secure fuse and return lifecyclePeng Fan1-0/+2
Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: use generic name ele(EdgeLockSecure Enclave)Peng Fan3-26/+28
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave code including comment, folder and API name to ELE to align. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-05Merge tag 'v2023.07-rc6' into nextTom Rini2-0/+13
Prepare v2023.07-rc6
2023-07-01ARM: arm11: Add C wrapper for allow_unaligned()Marek Vasut1-0/+12
Rename current assembler implementation of allow_unaligned() to arm11_arch_cp15_allow_unaligned() and add it into arm11.h header, then add C wrapper of allow_unaligned(). This fixes misbehavior when linking U-Boot, where the CPU specific allow_unaligned() implementation was ignored and instead the __weak allow_unaligned() implementation from lib/efi_loader/efi_setup.c was used, which led to "data abort" just before booting Linux via tftp, in efi_dp_from_file() -> path_to_uefi() -> utf16_put() . The problem is triggerd by c7c0ca37673 ("efi_loader: fix efi_dp_from_file()") . Adding the wrapper fixes the problem. Fixes: d47a774680d ("arm: arm11: allow unaligned memory access") Signed-off-by: Marek Vasut <marex@denx.de>
2023-07-01ARM: armv7: Add C wrapper for allow_unaligned()Marek Vasut1-0/+1
Rename current assembler implementation of allow_unaligned() to v7_arch_cp15_allow_unaligned() and add it into armv7.h header, then add C wrapper of allow_unaligned(). This fixes misbehavior when linking U-Boot on ARMv7a i.MX6Q, where the CPU specific allow_unaligned() implementation was ignored and instead the __weak allow_unaligned() implementation from lib/efi_loader/efi_setup.c was used, which led to "data abort" just before booting Linux via tftp, in efi_dp_from_file() -> path_to_uefi() -> utf16_put() . The problem is triggerd by c7c0ca37673 ("efi_loader: fix efi_dp_from_file()") . Adding the wrapper fixes the problem. Fixes: 78f90aaeecc ("arm: armv7: allow unaligned memory access") Signed-off-by: Marek Vasut <marex@denx.de>
2023-06-28arch/arm: meson: sm: introduce power domain functionsAlexey Romanov1-0/+30
This commit adds functions to manage secure power domain for Amlogic SoC's using smc functionality. Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230531093156.29240-2-avromanov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-06-28ARM: meson: add A1 supportIgor Prusov1-0/+20
Add support for Amlogic A1 SoC family. Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru> Signed-off-by: Evgeny Bachinin <eabachinin@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230505125639.3605-4-ivprusov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-06-12Merge tag 'xilinx-for-v2023.10-rc1' of ↵WIP/12Jun2023-nextTom Rini2-2/+2
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.10-rc1 global: - Use proper U-Boot project name Fix sparse warnings in zynqmp-clk, zynqmp handoff, board cmd: - Cover incorrect 0 length entries Versal NET: - Add bootmode logic - Support SPP production version - Add loadpdi command ZynqMP: - Clear pmufw node command ID handling - Change power domain behavior around zynqmp_pmufw_node() - Fix zynqmp cmd return values and pmufw command - Fix R5 tcm init and modes mmc: - Sync Versal NET emmc DT binding pcie: - Add support for ZynqMP PCIe root port video: - Add support for ZynqMP DP tools: - Fix debug message in relocate-rela
2023-06-12Merge tag v2023.07-rc4 into nextTom Rini19-841/+75
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-06-12global: Use proper project name U-BootMichal Simek2-2/+2
Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Qu Wenruo <wqu@suse.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
2023-06-07sunxi: Fix typo in include guardSam Edwards1-1/+1
Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-06-01arm64: Remove duplicated symbolsLeo Yan1-2/+0
When build U-boot with clang with using commands: $ make HOSTCC=clang xenguest_arm64_defconfig $ make HOSTCC=clang CROSS_COMPILE=aarch64-linux-gnu- \ CC="clang -target aarch64-linux-gnueabi" -j8 The compiler reports error: /tmp/start-acdf31.s:330:1: error: symbol '_start' is already defined _start: ^ Because the symbol '_start' has been defined twice, one is defined in arch/arm/cpu/armv8/start.S, another is defined in the header boot0-linux-kernel-header.h. To fix building failure, this patch removes the symbol '_start' from boot0-linux-kernel-header.h. Signed-off-by: Leo Yan <leo.yan@linaro.org>
2023-05-31arm: set alignment properly for asm funcsSam Edwards1-2/+2
ARM requires a 4-byte alignment on all ARM code (though this requirement is relaxed to 2-byte for some THUMB code) and we should be explicit about that here. GAS has its own fix for this[1] that forces proper alignment on any section containing assembled instructions, but this is not universal: Clang's and other gaslike assemblers lack this implicit alignment. Whether or not this is considered a bug in those assemblers, it is better to ask directly for what we want. [1]: https://sourceware.org/bugzilla/show_bug.cgi?id=12931 Signed-off-by: Sam Edwards <CFSworks@gmail.com>
2023-05-31arm: use asm-generic/unaligned.hJens Wiklander1-19/+2
Arm duplicates the content of asm-generic/unaligned.h, so use that file directly instead. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-05-31include: Remove unused header filesTom Rini12-757/+0
As part of various code clean-ups we have on occasion missed removing unused header files. None of these files are referenced anywhere else at this point. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-31imx: fix header inclusion guardsAndre Przywara3-3/+3
It seems like the header inclusion guards for some IMX related headers were misspelled or got out of sync. Make the preprocessor symbols for the #ifndef and #define lines the same, so that the double inclusion protection works as expected. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-05-31arm: Remove ti816x_evm board and ti816x SoC supportTom Rini11-615/+1
This platform is currently unmaintained and untested, so remove it. Further, as it is the only TI816X SoC example, remove related files as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-25Merge tag 'u-boot-imx-20230525' of ↵WIP/25May2023Tom Rini16-840/+52
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20230525 ------------------- - i.MX93 series - Fixes CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16412
2023-05-21ddr: imx93: update the ddr init to support mult setpointsJacky Bai2-2/+21
Update the DDR init flow for multi-setpoint support on i.MX93. A new fsp_cfg struct need to be added in the timing file to store the diff part of the DDRC and DRAM MR register for each setpoint. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li1-0/+2
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: add i.MX93 variants supportPeng Fan2-1/+18
According to datasheet, iMX93 has fused parts with CORE1 or NPU or both disabled. So update code to support it, the kernel device tree runtime update will be added in future patches. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: Get market segment and speed gradingPeng Fan1-0/+3
Get the chip's market segment and speed grading from fuse and print them in boot log as other i.MX series. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: simplify clk settingsPeng Fan1-0/+6
Simplify the clk root settings with an array Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx: move imx8 sci header file to include/firmware/imxPeng Fan10-837/+2
Move imx8 sci header file to include/firmware/imx, then we could use build macro to reuse some i.MX8 drivers for i.MX9, such as drivers/cpu/imx8_cpu.c. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
2023-05-19rockchip: rk3588-rock-5b: Enable boot from SPI NOR flashJonas Karlman1-0/+1
Add sfc and flash node to device tree and config options to enable support for booting from SPI NOR flash on Radxa ROCK 5 Model B. Similar to RK3568 the BootRom in RK3588 can read all data and look for idbloader at 0x8000, same as on SD and eMMC. Use the rksd format and modify the mkimage offset to generate a bootable u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The FIT image is loaded from 0x60000. => sf probe SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1492992 bytes read in 129 ms (11 MiB/s) => sf update $fileaddr 0 $filesize device 0 offset 0x0, size 0x16c800 1300480 bytes written, 192512 bytes skipped in 11.103s, speed 137694 B/s The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does not match the expected value of 3 (SPINOR) used by other SoCs. Instead a value of 6 is read back, add a new enum value to handle this new bootsource id. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17reset: rockchip: implement rk3588 lookup tableEugen Hristev1-0/+21
The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-02imx6: clock: add support to get LCD pixel clock rateDario Binacchi1-0/+2
Add the get_lcd_clk() function to get the LCD pixel clock rate. The patch has been tested on imx6ul platform. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-28gpio: axp/sunxi: Remove virtual VBUS detection GPIOSamuel Holland1-1/+0
Now that this functionality is modeled using the device tree and regulator uclass, the named GPIO is not referenced anywhere. Remove it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-25armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is presentmeitao1-2/+8
u-boot could be run at EL1/EL2/EL3. so we set it as same as EL1 does. otherwise it will hang when enable mmu, that is what we encounter in our SOC. Signed-off-by: meitao <meitaogao@asrmicro.com> [ Paul: pick from the Android tree. Rebase to the upstream ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link: https://android.googlesource.com/platform/external/u-boot/+/3bf38943aeab4700c2319bff2a1477d99c6afd2f
2023-04-25arm64: Use level-2 for largest block mappings when FEAT_HAFDBS is presentMarc Zyngier1-0/+1
In order to make invalidation by VA more efficient, set the largest block mapping to 2MB, mapping it onto level-2. This has no material impact on u-boot's runtime performance, and allows a huge speedup when cleaning the cache. Signed-off-by: Marc Zyngier <maz@kernel.org> [ Paul: pick from the Android tree. Rebase to the upstream ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link: https://android.googlesource.com/platform/external/u-boot/+/417a73581a72ff6d6ee4b0938117b8a23e32f7e8
2023-04-25arm64: Use FEAT_HAFDBS to track dirty pages when availableMarc Zyngier2-4/+11
Some recent arm64 cores have a facility that allows the page table walker to track the dirty state of a page. This makes it really efficient to perform CMOs by VA as we only need to look at dirty pages. Signed-off-by: Marc Zyngier <maz@kernel.org> [ Paul: pick from the Android tree. Rebase to the upstream ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link: https://android.googlesource.com/platform/external/u-boot/+/3c433724e6f830a6b2edd5ec3d4a504794887263
2023-04-21rockchip: rk3588: Add support for sdmmc clocks in SPLJonas Karlman2-2/+18
Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-12sunxi: arm64: boot0.h: runtime check for RVBAR addressAndre Przywara1-4/+10
Some SoCs of the H616 family use a die variant, that puts some CPU power and reset control registers at a different address. There are examples of two instances of the same board, using different die revisions of the otherwise same H313 SoC. We need to write to a register in that block *very* early in the SPL boot, to switch the core to AArch64. Since the devices are otherwise indistinguishable, let the SPL code read that die variant and use the respective RVBAR address based on that. That is a bit tricky, since we need to do that in hand-coded AArch32 machine language, shared by all 64-bit SoCs. To avoid build dependencies in this mess, we always provide two addresses to choose from, and just give identical values for all other SoCs. This allows the same code to run on all 64-bit SoCs, and controls this switch behaviour purely from Kconfig. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12sunxi: boot0.h: allow RVBAR MMIO address customisationAndre Przywara1-5/+2
To switch the ARMv8 Allwinner SoCs into the 64-bit AArch64 ISA, we need to program the 64-bit start code address into an MMIO mapped register that shadows the architectural RVBAR register. This address is SoC specific, with just two versions out there so far. Now a third address emerged, on a *variant* of an existing SoC (H616). Change the boot0.h start code to make this address a Kconfig selectable option, to allow easier maintenance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12sunxi: Add TPR2 parameter for H616 DRAM driverJernej Skrabec1-0/+1
It turns out that some H616 and related SoCs (like H313) need TPR2 parameter for proper working. Add it. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Parameterize "unknown feature" in H616 DRAM driverJernej Skrabec1-0/+1
Part of the code, previously known as "unknown feature", also doesn't have constant values. They are derived from TPR0 parameter in vendor DRAM code. Let's move that code to separate function and introduce TPR0 parameter here too, to ease adding new boards. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Parameterize bit delay code in H616 DRAM driverJernej Skrabec1-0/+3
These values are highly board specific and thus make sense to add parameter for them. To ease adding support for new boards, let's make them same as in vendor DRAM settings. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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