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authorTom Rini <trini@konsulko.com>2023-05-16 12:34:47 -0400
committerTom Rini <trini@konsulko.com>2023-05-31 12:31:47 -0400
commitf1671205fa44084b334027a267c86e5be2ea7c1a (patch)
treecfa3fdb741c0a333fc2601153a10ef8ca0870ca0 /arch/arm/include/asm
parenta179217e68e5c0c91004b1084e04091a80a6bb7e (diff)
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include: Remove unused header files
As part of various code clean-ups we have on occasion missed removing unused header files. None of these files are referenced anywhere else at this point. Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-bcmcygnus/configs.h18
-rw-r--r--arch/arm/include/asm/arch-bcmnsp/configs.h17
-rw-r--r--arch/arm/include/asm/arch-imxrt/imxrt.h10
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/gpio_grp.h39
-rw-r--r--arch/arm/include/asm/arch-mx27/mxcmmc.h11
-rw-r--r--arch/arm/include/asm/arch-mx6/opos6ul.h11
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-uartapp.h219
-rw-r--r--arch/arm/include/asm/arch-omap3/omap3-regs.h78
-rw-r--r--arch/arm/include/asm/arch-omap5/mux_omap5.h317
-rw-r--r--arch/arm/include/asm/iproc-common/configs.h14
-rw-r--r--arch/arm/include/asm/iproc-common/iproc_sdhci.h12
-rw-r--r--arch/arm/include/asm/kona-common/kona_sdhci.h11
12 files changed, 0 insertions, 757 deletions
diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h
deleted file mode 100644
index fd8dad3..0000000
--- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014-2017 Broadcom.
- */
-
-#ifndef __ARCH_CONFIGS_H
-#define __ARCH_CONFIGS_H
-
-#include <asm/iproc-common/configs.h>
-
-/* uArchitecture specifics */
-
-/* Serial Info */
-#define CFG_SYS_NS16550_CLK 100000000
-#define CFG_SYS_NS16550_CLK_DIV 54
-#define CFG_SYS_NS16550_COM3 0x18023000
-
-#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h
deleted file mode 100644
index 0d4baf3..0000000
--- a/arch/arm/include/asm/arch-bcmnsp/configs.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Broadcom Corporation.
- */
-
-#ifndef __ARCH_CONFIGS_H
-#define __ARCH_CONFIGS_H
-
-#include <asm/iproc-common/configs.h>
-
-/* uArchitecture specifics */
-
-/* Serial Info */
-#define CFG_SYS_NS16550_CLK 0x03b9aca0
-#define CFG_SYS_NS16550_COM1 0x18000300
-
-#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-imxrt/imxrt.h b/arch/arm/include/asm/arch-imxrt/imxrt.h
deleted file mode 100644
index 14f7c76..0000000
--- a/arch/arm/include/asm/arch-imxrt/imxrt.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#ifndef _ASM_ARCH_IMXRT_H
-#define _ASM_ARCH_IMXRT_H
-
-#endif /* _ASM_ARCH_IMXRT_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
deleted file mode 100644
index 762bbee..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * LPC32xx GPIO interface macro for pin mapping.
- *
- * (C) Copyright 2015 DENX Software Engineering GmbH
- * Written-by: Sylvain Lemieux <slemieux@@tycoint.com>
- */
-
-#ifndef _LPC32XX_GPIO_GRP_H
-#define _LPC32XX_GPIO_GRP_H
-
-/*
- * Macro to map the pin for the lpc32xx_gpio driver.
- * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
- * mapping is done per register, as group of 32.
- * (see drivers/gpio/lpc32xx_gpio.c for details).
- * - macros can be use with the following pins:
- * P0.0 - P0.7
- * P1.0 - P1.23
- * P2.0 - P2.12
- * P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28
- * P3 GPO_0 - GPO_23
- * P3 GPIO_0 - GPIO_5 (output register only)
- */
-#define LPC32XX_GPIO_P0_GRP 0
-#define LPC32XX_GPIO_P1_GRP 32
-#define LPC32XX_GPIO_P2_GRP 64
-#define LPC32XX_GPO_P3_GRP 96
-#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
-#define LPC32XX_GPI_P3_GRP 128
-
-/*
- * A specific GPIO can be selected with this macro
- * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1)
- * See the LPC32x0 User's guide for GPIO group numbers
- */
-#define LPC32XX_GPIO(x, y) ((x) + (y))
-
-#endif /* _LPC32XX_GPIO_GRP_H */
diff --git a/arch/arm/include/asm/arch-mx27/mxcmmc.h b/arch/arm/include/asm/arch-mx27/mxcmmc.h
deleted file mode 100644
index 52fb0ab..0000000
--- a/arch/arm/include/asm/arch-mx27/mxcmmc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- */
-
-#ifndef ASM_ARCH_MXCMMC_H
-#define ASM_ARCH_MXCMMC_H
-
-int mxc_mmc_init(struct bd_info *bis);
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx6/opos6ul.h b/arch/arm/include/asm/arch-mx6/opos6ul.h
deleted file mode 100644
index b55a54c..0000000
--- a/arch/arm/include/asm/arch-mx6/opos6ul.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Armadeus Systems
- */
-
-#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__
-#define __ARCH_ARM_MX6UL_OPOS6UL_H__
-
-int opos6ul_board_late_init(void);
-
-#endif
diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
deleted file mode 100644
index d89cf27..0000000
--- a/arch/arm/include/asm/arch-mxs/regs-uartapp.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Freescale MXS UARTAPP Register Definitions
- *
- * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
- *
- * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-#ifndef __ARCH_ARM___MXS_UARTAPP_H
-#define __ARCH_ARM___MXS_UARTAPP_H
-
-#include <asm/mach-imx/regs-common.h>
-
-#ifndef __ASSEMBLY__
-struct mxs_uartapp_regs {
- mxs_reg_32(hw_uartapp_ctrl0)
- mxs_reg_32(hw_uartapp_ctrl1)
- mxs_reg_32(hw_uartapp_ctrl2)
- mxs_reg_32(hw_uartapp_linectrl)
- mxs_reg_32(hw_uartapp_linectrl2)
- mxs_reg_32(hw_uartapp_intr)
- mxs_reg_32(hw_uartapp_data)
- mxs_reg_32(hw_uartapp_stat)
- mxs_reg_32(hw_uartapp_debug)
- mxs_reg_32(hw_uartapp_version)
- mxs_reg_32(hw_uartapp_autobaud)
-};
-#endif
-
-#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31)
-#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30)
-#define UARTAPP_CTRL0_RUN_MASK (1 << 29)
-#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28)
-#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27)
-#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16
-#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16)
-#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0
-#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF
-
-#define UARTAPP_CTRL1_RUN_MASK (1 << 28)
-
-#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0
-#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF
-
-#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31)
-#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30)
-#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29)
-#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28)
-#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27)
-#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26)
-#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25)
-#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24)
-#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
-#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20)
-
-#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20)
-#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20)
-#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16
-#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16)
-#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16)
-#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15)
-#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14)
-#define UARTAPP_CTRL2_OUT2_MASK (1 << 13)
-#define UARTAPP_CTRL2_OUT1_MASK (1 << 12)
-#define UARTAPP_CTRL2_RTS_MASK (1 << 11)
-#define UARTAPP_CTRL2_DTR_MASK (1 << 10)
-#define UARTAPP_CTRL2_RXE_MASK (1 << 9)
-#define UARTAPP_CTRL2_TXE_MASK (1 << 8)
-#define UARTAPP_CTRL2_LBE_MASK (1 << 7)
-#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6)
-
-#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2)
-#define UARTAPP_CTRL2_SIREN_MASK (1 << 1)
-#define UARTAPP_CTRL2_UARTEN_MASK 0x01
-
-#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16
-#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16)
-#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6
-
-#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8
-#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8)
-#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
-
-#define UARTAPP_LINECTRL_SPS_MASK (1 << 7)
-#define UARTAPP_LINECTRL_WLEN_OFFSET 5
-#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5)
-#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5)
-#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5)
-#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5)
-#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5)
-
-#define UARTAPP_LINECTRL_FEN_MASK (1 << 4)
-#define UARTAPP_LINECTRL_STP2_MASK (1 << 3)
-#define UARTAPP_LINECTRL_EPS_MASK (1 << 2)
-#define UARTAPP_LINECTRL_PEN_MASK (1 << 1)
-#define UARTAPP_LINECTRL_BRK_MASK 1
-
-#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16
-#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16)
-#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6
-
-#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8
-#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8)
-#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
-
-#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7)
-#define UARTAPP_LINECTRL2_WLEN_OFFSET 5
-#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5)
-#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5)
-#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5)
-#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5)
-#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5)
-
-#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4)
-#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3)
-#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2)
-#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1)
-
-#define UARTAPP_INTR_ABDIEN_MASK (1 << 27)
-#define UARTAPP_INTR_OEIEN_MASK (1 << 26)
-#define UARTAPP_INTR_BEIEN_MASK (1 << 25)
-#define UARTAPP_INTR_PEIEN_MASK (1 << 24)
-#define UARTAPP_INTR_FEIEN_MASK (1 << 23)
-#define UARTAPP_INTR_RTIEN_MASK (1 << 22)
-#define UARTAPP_INTR_TXIEN_MASK (1 << 21)
-#define UARTAPP_INTR_RXIEN_MASK (1 << 20)
-#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19)
-#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18)
-#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17)
-#define UARTAPP_INTR_RIMIEN_MASK (1 << 16)
-
-#define UARTAPP_INTR_ABDIS_MASK (1 << 11)
-#define UARTAPP_INTR_OEIS_MASK (1 << 10)
-#define UARTAPP_INTR_BEIS_MASK (1 << 9)
-#define UARTAPP_INTR_PEIS_MASK (1 << 8)
-#define UARTAPP_INTR_FEIS_MASK (1 << 7)
-#define UARTAPP_INTR_RTIS_MASK (1 << 6)
-#define UARTAPP_INTR_TXIS_MASK (1 << 5)
-#define UARTAPP_INTR_RXIS_MASK (1 << 4)
-#define UARTAPP_INTR_DSRMIS_MASK (1 << 3)
-#define UARTAPP_INTR_DCDMIS_MASK (1 << 2)
-#define UARTAPP_INTR_CTSMIS_MASK (1 << 1)
-#define UARTAPP_INTR_RIMIS_MASK 0x1
-
-#define UARTAPP_DATA_DATA_OFFSET 0
-#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF
-#define UARTAPP_STAT_PRESENT_MASK (1 << 31)
-#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31)
-#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31)
-
-#define UARTAPP_STAT_HISPEED_MASK (1 << 30)
-#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30)
-#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30)
-
-#define UARTAPP_STAT_BUSY_MASK (1 << 29)
-#define UARTAPP_STAT_CTS_MASK (1 << 28)
-#define UARTAPP_STAT_TXFE_MASK (1 << 27)
-#define UARTAPP_STAT_RXFF_MASK (1 << 26)
-#define UARTAPP_STAT_TXFF_MASK (1 << 25)
-#define UARTAPP_STAT_RXFE_MASK (1 << 24)
-#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20
-#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20)
-
-#define UARTAPP_STAT_OERR_MASK (1 << 19)
-#define UARTAPP_STAT_BERR_MASK (1 << 18)
-#define UARTAPP_STAT_PERR_MASK (1 << 17)
-#define UARTAPP_STAT_FERR_MASK (1 << 16)
-#define UARTAPP_STAT_RXCOUNT_OFFSET 0
-#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF
-
-#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16
-#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16)
-
-#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10
-#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10)
-
-#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5)
-#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4)
-#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3)
-#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2)
-#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1)
-#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01
-
-#define UARTAPP_VERSION_MAJOR_OFFSET 24
-#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24)
-
-#define UARTAPP_VERSION_MINOR_OFFSET 16
-#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16)
-
-#define UARTAPP_VERSION_STEP_OFFSET 0
-#define UARTAPP_VERSION_STEP_MASK 0xFFFF
-
-#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24
-#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24)
-
-#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16
-#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16)
-
-#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4)
-#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3)
-#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2)
-#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1)
-#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01
-#endif /* __ARCH_ARM___UARTAPP_H */
diff --git a/arch/arm/include/asm/arch-omap3/omap3-regs.h b/arch/arm/include/asm/arch-omap3/omap3-regs.h
deleted file mode 100644
index 7b3c6c7..0000000
--- a/arch/arm/include/asm/arch-omap3/omap3-regs.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it>
- */
-
-#ifndef _OMAP3_REGS_H
-#define _OMAP3_REGS_H
-
-/*
- * Register definitions for OMAP3 processors.
- */
-
-/*
- * GPMC_CONFIG1 - GPMC_CONFIG7
- */
-
-/* Values for GPMC_CONFIG1 - signal control parameters */
-#define WRAPBURST (1 << 31)
-#define READMULTIPLE (1 << 30)
-#define READTYPE (1 << 29)
-#define WRITEMULTIPLE (1 << 28)
-#define WRITETYPE (1 << 27)
-#define CLKACTIVATIONTIME(x) (((x) & 3) << 25)
-#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23)
-#define WAITREADMONITORING (1 << 22)
-#define WAITWRITEMONITORING (1 << 21)
-#define WAITMONITORINGTIME(x) (((x) & 3) << 18)
-#define WAITPINSELECT(x) (((x) & 3) << 16)
-#define DEVICESIZE(x) (((x) & 3) << 12)
-#define DEVICESIZE_8BIT DEVICESIZE(0)
-#define DEVICESIZE_16BIT DEVICESIZE(1)
-#define DEVICETYPE(x) (((x) & 3) << 10)
-#define DEVICETYPE_NOR DEVICETYPE(0)
-#define DEVICETYPE_NAND DEVICETYPE(2)
-#define MUXADDDATA (1 << 9)
-#define TIMEPARAGRANULARITY (1 << 4)
-#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0)
-
-/* Values for GPMC_CONFIG2 - CS timing */
-#define CSWROFFTIME(x) (((x) & 0x1f) << 16)
-#define CSRDOFFTIME(x) (((x) & 0x1f) << 8)
-#define CSEXTRADELAY (1 << 7)
-#define CSONTIME(x) (((x) & 0xf) << 0)
-
-/* Values for GPMC_CONFIG3 - nADV timing */
-#define ADVWROFFTIME(x) (((x) & 0x1f) << 16)
-#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8)
-#define ADVEXTRADELAY (1 << 7)
-#define ADVONTIME(x) (((x) & 0xf) << 0)
-
-/* Values for GPMC_CONFIG4 - nWE and nOE timing */
-#define WEOFFTIME(x) (((x) & 0x1f) << 24)
-#define WEEXTRADELAY (1 << 23)
-#define WEONTIME(x) (((x) & 0xf) << 16)
-#define OEOFFTIME(x) (((x) & 0x1f) << 8)
-#define OEEXTRADELAY (1 << 7)
-#define OEONTIME(x) (((x) & 0xf) << 0)
-
-/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */
-#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24)
-#define RDACCESSTIME(x) (((x) & 0x1f) << 16)
-#define WRCYCLETIME(x) (((x) & 0x1f) << 8)
-#define RDCYCLETIME(x) (((x) & 0x1f) << 0)
-
-/* Values for GPMC_CONFIG6 - misc timings */
-#define WRACCESSTIME(x) (((x) & 0x1f) << 24)
-#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16)
-#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8)
-#define CYCLE2CYCLESAMECSEN (1 << 7)
-#define CYCLE2CYCLEDIFFCSEN (1 << 6)
-#define BUSTURNAROUND(x) (((x) & 0xf) << 0)
-
-/* Values for GPMC_CONFIG7 - CS address mapping configuration */
-#define MASKADDRESS(x) (((x) & 0xf) << 8)
-#define CSVALID (1 << 6)
-#define BASEADDRESS(x) (((x) & 0x3f) << 0)
-
-#endif /* _OMAP3_REGS_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h
deleted file mode 100644
index 2460646..0000000
--- a/arch/arm/include/asm/arch-omap5/mux_omap5.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated
- * Richard Woodruff <r-woodruff2@ti.com>
- * Aneesh V <aneesh@ti.com>
- * Balaji Krishnamoorthy <balajitk@ti.com>
- */
-#ifndef _MUX_OMAP5_H_
-#define _MUX_OMAP5_H_
-
-#include <asm/types.h>
-
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_PD (1 << 12)
-#define OFF_PU (3 << 12)
-#define OFF_OUT_PTD (0 << 10)
-#define OFF_OUT_PTU (2 << 10)
-#define OFF_IN (1 << 10)
-#define OFF_OUT (0 << 10)
-#define OFF_EN (1 << 9)
-#else
-#define OFF_PD (0 << 12)
-#define OFF_PU (0 << 12)
-#define OFF_OUT_PTD (0 << 10)
-#define OFF_OUT_PTU (0 << 10)
-#define OFF_IN (0 << 10)
-#define OFF_OUT (0 << 10)
-#define OFF_EN (0 << 9)
-#endif
-
-#define IEN (1 << 8)
-#define IDIS (0 << 8)
-#define PTU (3 << 3)
-#define PTD (1 << 3)
-#define EN (1 << 3)
-#define DIS (0 << 3)
-
-#define M0 0
-#define M1 1
-#define M2 2
-#define M3 3
-#define M4 4
-#define M5 5
-#define M6 6
-#define M7 7
-
-#define SAFE_MODE M7
-
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
-#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
-#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
-#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
-#else
-#define OFF_IN_PD 0
-#define OFF_IN_PU 0
-#define OFF_OUT_PD 0
-#define OFF_OUT_PU 0
-#endif
-
-#define CORE_REVISION 0x0000
-#define CORE_HWINFO 0x0004
-#define CORE_SYSCONFIG 0x0010
-#define EMMC_CLK 0x0040
-#define EMMC_CMD 0x0042
-#define EMMC_DATA0 0x0044
-#define EMMC_DATA1 0x0046
-#define EMMC_DATA2 0x0048
-#define EMMC_DATA3 0x004a
-#define EMMC_DATA4 0x004c
-#define EMMC_DATA5 0x004e
-#define EMMC_DATA6 0x0050
-#define EMMC_DATA7 0x0052
-#define C2C_CLKOUT0 0x0054
-#define C2C_CLKOUT1 0x0056
-#define C2C_CLKIN0 0x0058
-#define C2C_CLKIN1 0x005a
-#define C2C_DATAIN0 0x005c
-#define C2C_DATAIN1 0x005e
-#define C2C_DATAIN2 0x0060
-#define C2C_DATAIN3 0x0062
-#define C2C_DATAIN4 0x0064
-#define C2C_DATAIN5 0x0066
-#define C2C_DATAIN6 0x0068
-#define C2C_DATAIN7 0x006a
-#define C2C_DATAOUT0 0x006c
-#define C2C_DATAOUT1 0x006e
-#define C2C_DATAOUT2 0x0070
-#define C2C_DATAOUT3 0x0072
-#define C2C_DATAOUT4 0x0074
-#define C2C_DATAOUT5 0x0076
-#define C2C_DATAOUT6 0x0078
-#define C2C_DATAOUT7 0x007a
-#define C2C_DATA8 0x007c
-#define C2C_DATA9 0x007e
-#define C2C_DATA10 0x0080
-#define C2C_DATA11 0x0082
-#define C2C_DATA12 0x0084
-#define C2C_DATA13 0x0086
-#define C2C_DATA14 0x0088
-#define C2C_DATA15 0x008a
-#define LLIA_WAKEREQOUT 0x008c
-#define LLIB_WAKEREQOUT 0x008e
-#define HSI1_ACREADY 0x0090
-#define HSI1_CAREADY 0x0092
-#define HSI1_ACWAKE 0x0094
-#define HSI1_CAWAKE 0x0096
-#define HSI1_ACFLAG 0x0098
-#define HSI1_ACDATA 0x009a
-#define HSI1_CAFLAG 0x009c
-#define HSI1_CADATA 0x009e
-#define UART1_TX 0x00a0
-#define UART1_CTS 0x00a2
-#define UART1_RX 0x00a4
-#define UART1_RTS 0x00a6
-#define HSI2_CAREADY 0x00a8
-#define HSI2_ACREADY 0x00aa
-#define HSI2_CAWAKE 0x00ac
-#define HSI2_ACWAKE 0x00ae
-#define HSI2_CAFLAG 0x00b0
-#define HSI2_CADATA 0x00b2
-#define HSI2_ACFLAG 0x00b4
-#define HSI2_ACDATA 0x00b6
-#define UART2_RTS 0x00b8
-#define UART2_CTS 0x00ba
-#define UART2_RX 0x00bc
-#define UART2_TX 0x00be
-#define USBB1_HSIC_STROBE 0x00c0
-#define USBB1_HSIC_DATA 0x00c2
-#define USBB2_HSIC_STROBE 0x00c4
-#define USBB2_HSIC_DATA 0x00c6
-#define TIMER10_PWM_EVT 0x00c8
-#define DSIPORTA_TE0 0x00ca
-#define DSIPORTA_LANE0X 0x00cc
-#define DSIPORTA_LANE0Y 0x00ce
-#define DSIPORTA_LANE1X 0x00d0
-#define DSIPORTA_LANE1Y 0x00d2
-#define DSIPORTA_LANE2X 0x00d4
-#define DSIPORTA_LANE2Y 0x00d6
-#define DSIPORTA_LANE3X 0x00d8
-#define DSIPORTA_LANE3Y 0x00da
-#define DSIPORTA_LANE4X 0x00dc
-#define DSIPORTA_LANE4Y 0x00de
-#define DSIPORTC_LANE0X 0x00e0
-#define DSIPORTC_LANE0Y 0x00e2
-#define DSIPORTC_LANE1X 0x00e4
-#define DSIPORTC_LANE1Y 0x00e6
-#define DSIPORTC_LANE2X 0x00e8
-#define DSIPORTC_LANE2Y 0x00ea
-#define DSIPORTC_LANE3X 0x00ec
-#define DSIPORTC_LANE3Y 0x00ee
-#define DSIPORTC_LANE4X 0x00f0
-#define DSIPORTC_LANE4Y 0x00f2
-#define DSIPORTC_TE0 0x00f4
-#define TIMER9_PWM_EVT 0x00f6
-#define I2C4_SCL 0x00f8
-#define I2C4_SDA 0x00fa
-#define MCSPI2_CLK 0x00fc
-#define MCSPI2_SIMO 0x00fe
-#define MCSPI2_SOMI 0x0100
-#define MCSPI2_CS0 0x0102
-#define RFBI_DATA15 0x0104
-#define RFBI_DATA14 0x0106
-#define RFBI_DATA13 0x0108
-#define RFBI_DATA12 0x010a
-#define RFBI_DATA11 0x010c
-#define RFBI_DATA10 0x010e
-#define RFBI_DATA9 0x0110
-#define RFBI_DATA8 0x0112
-#define RFBI_DATA7 0x0114
-#define RFBI_DATA6 0x0116
-#define RFBI_DATA5 0x0118
-#define RFBI_DATA4 0x011a
-#define RFBI_DATA3 0x011c
-#define RFBI_DATA2 0x011e
-#define RFBI_DATA1 0x0120
-#define RFBI_DATA0 0x0122
-#define RFBI_WE 0x0124
-#define RFBI_CS0 0x0126
-#define RFBI_A0 0x0128
-#define RFBI_RE 0x012a
-#define RFBI_HSYNC0 0x012c
-#define RFBI_TE_VSYNC0 0x012e
-#define GPIO6_182 0x0130
-#define GPIO6_183 0x0132
-#define GPIO6_184 0x0134
-#define GPIO6_185 0x0136
-#define GPIO6_186 0x0138
-#define GPIO6_187 0x013a
-#define HDMI_CEC 0x013c
-#define HDMI_HPD 0x013e
-#define HDMI_DDC_SCL 0x0140
-#define HDMI_DDC_SDA 0x0142
-#define CSIPORTC_LANE0X 0x0144
-#define CSIPORTC_LANE0Y 0x0146
-#define CSIPORTC_LANE1X 0x0148
-#define CSIPORTC_LANE1Y 0x014a
-#define CSIPORTB_LANE0X 0x014c
-#define CSIPORTB_LANE0Y 0x014e
-#define CSIPORTB_LANE1X 0x0150
-#define CSIPORTB_LANE1Y 0x0152
-#define CSIPORTB_LANE2X 0x0154
-#define CSIPORTB_LANE2Y 0x0156
-#define CSIPORTA_LANE0X 0x0158
-#define CSIPORTA_LANE0Y 0x015a
-#define CSIPORTA_LANE1X 0x015c
-#define CSIPORTA_LANE1Y 0x015e
-#define CSIPORTA_LANE2X 0x0160
-#define CSIPORTA_LANE2Y 0x0162
-#define CSIPORTA_LANE3X 0x0164
-#define CSIPORTA_LANE3Y 0x0166
-#define CSIPORTA_LANE4X 0x0168
-#define CSIPORTA_LANE4Y 0x016a
-#define CAM_SHUTTER 0x016c
-#define CAM_STROBE 0x016e
-#define CAM_GLOBALRESET 0x0170
-#define TIMER11_PWM_EVT 0x0172
-#define TIMER5_PWM_EVT 0x0174
-#define TIMER6_PWM_EVT 0x0176
-#define TIMER8_PWM_EVT 0x0178
-#define I2C3_SCL 0x017a
-#define I2C3_SDA 0x017c
-#define GPIO8_233 0x017e
-#define GPIO8_234 0x0180
-#define ABE_CLKS 0x0182
-#define ABEDMIC_DIN1 0x0184
-#define ABEDMIC_DIN2 0x0186
-#define ABEDMIC_DIN3 0x0188
-#define ABEDMIC_CLK1 0x018a
-#define ABEDMIC_CLK2 0x018c
-#define ABEDMIC_CLK3 0x018e
-#define ABESLIMBUS1_CLOCK 0x0190
-#define ABESLIMBUS1_DATA 0x0192
-#define ABEMCBSP2_DR 0x0194
-#define ABEMCBSP2_DX 0x0196
-#define ABEMCBSP2_FSX 0x0198
-#define ABEMCBSP2_CLKX 0x019a
-#define ABEMCPDM_UL_DATA 0x019c
-#define ABEMCPDM_DL_DATA 0x019e
-#define ABEMCPDM_FRAME 0x01a0
-#define ABEMCPDM_LB_CLK 0x01a2
-#define WLSDIO_CLK 0x01a4
-#define WLSDIO_CMD 0x01a6
-#define WLSDIO_DATA0 0x01a8
-#define WLSDIO_DATA1 0x01aa
-#define WLSDIO_DATA2 0x01ac
-#define WLSDIO_DATA3 0x01ae
-#define UART5_RX 0x01b0
-#define UART5_TX 0x01b2
-#define UART5_CTS 0x01b4
-#define UART5_RTS 0x01b6
-#define I2C2_SCL 0x01b8
-#define I2C2_SDA 0x01ba
-#define MCSPI1_CLK 0x01bc
-#define MCSPI1_SOMI 0x01be
-#define MCSPI1_SIMO 0x01c0
-#define MCSPI1_CS0 0x01c2
-#define MCSPI1_CS1 0x01c4
-#define I2C5_SCL 0x01c6
-#define I2C5_SDA 0x01c8
-#define PERSLIMBUS2_CLOCK 0x01ca
-#define PERSLIMBUS2_DATA 0x01cc
-#define UART6_TX 0x01ce
-#define UART6_RX 0x01d0
-#define UART6_CTS 0x01d2
-#define UART6_RTS 0x01d4
-#define UART3_CTS_RCTX 0x01d6
-#define UART3_RTS_IRSD 0x01d8
-#define UART3_TX_IRTX 0x01da
-#define UART3_RX_IRRX 0x01dc
-#define USBB3_HSIC_STROBE 0x01de
-#define USBB3_HSIC_DATA 0x01e0
-#define SDCARD_CLK 0x01e2
-#define SDCARD_CMD 0x01e4
-#define SDCARD_DATA2 0x01e6
-#define SDCARD_DATA3 0x01e8
-#define SDCARD_DATA0 0x01ea
-#define SDCARD_DATA1 0x01ec
-#define USBD0_HS_DP 0x01ee
-#define USBD0_HS_DM 0x01f0
-#define I2C1_PMIC_SCL 0x01f2
-#define I2C1_PMIC_SDA 0x01f4
-#define USBD0_SS_RX 0x01f6
-
-#define LLIA_WAKEREQIN 0x0040
-#define LLIB_WAKEREQIN 0x0042
-#define DRM_EMU0 0x0044
-#define DRM_EMU1 0x0046
-#define JTAG_NTRST 0x0048
-#define JTAG_TCK 0x004a
-#define JTAG_RTCK 0x004c
-#define JTAG_TMSC 0x004e
-#define JTAG_TDI 0x0050
-#define JTAG_TDO 0x0052
-#define SYS_32K 0x0054
-#define FREF_CLK_IOREQ 0x0056
-#define FREF_CLK0_OUT 0x0058
-#define FREF_CLK1_OUT 0x005a
-#define FREF_CLK2_OUT 0x005c
-#define FREF_CLK2_REQ 0x005e
-#define FREF_CLK1_REQ 0x0060
-#define SYS_NRESPWRON 0x0062
-#define SYS_NRESWARM 0x0064
-#define SYS_PWR_REQ 0x0066
-#define SYS_NIRQ1 0x0068
-#define SYS_NIRQ2 0x006a
-#define SR_PMIC_SCL 0x006c
-#define SR_PMIC_SDA 0x006e
-#define SYS_BOOT0 0x0070
-#define SYS_BOOT1 0x0072
-#define SYS_BOOT2 0x0074
-#define SYS_BOOT3 0x0076
-#define SYS_BOOT4 0x0078
-#define SYS_BOOT5 0x007a
-
-#endif /* _MUX_OMAP5_H_ */
diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h
deleted file mode 100644
index ce831bc..0000000
--- a/arch/arm/include/asm/iproc-common/configs.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Broadcom Corporation.
- */
-
-#ifndef __IPROC_COMMON_CONFIGS_H
-#define __IPROC_COMMON_CONFIGS_H
-
-#include <linux/stringify.h>
-
-/* Memory Info */
-#define CFG_SYS_SDRAM_BASE 0x61000000
-
-#endif /* __IPROC_COMMON_CONFIGS_H */
diff --git a/arch/arm/include/asm/iproc-common/iproc_sdhci.h b/arch/arm/include/asm/iproc-common/iproc_sdhci.h
deleted file mode 100644
index 4e29921..0000000
--- a/arch/arm/include/asm/iproc-common/iproc_sdhci.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: <SPDX License Expression> */
-/*
- * Copyright 2019 Broadcom
- *
- */
-
-#ifndef __IPROC_SDHCI_H
-#define __IPROC_SDHCI_H
-
-int iproc_sdhci_init(int dev_index, u32 quirks);
-
-#endif
diff --git a/arch/arm/include/asm/kona-common/kona_sdhci.h b/arch/arm/include/asm/kona-common/kona_sdhci.h
deleted file mode 100644
index 22db651..0000000
--- a/arch/arm/include/asm/kona-common/kona_sdhci.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Broadcom Corporation.
- */
-
-#ifndef __KONA_SDHCI_H
-#define __KONA_SDHCI_H
-
-int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks);
-
-#endif