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2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"WIP/20May2024-nextTom Rini1-1/+1
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini1-1/+1
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07board: freescale: Remove <common.h> and add needed includesTom Rini1-1/+1
Remove <common.h> from this board vendor directory and when needed add missing include files directly. Acked-by: Jason Liu <jason.hui.liu@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-13imx: imx8m: add CAAM_BASE_ADDRPeng Fan1-0/+1
Add CAAM_BASE_ADDR which will be used by priblob.c Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: bootaux: change names of MACROs used to boot MCU on iMX devicesPeng Fan1-1/+1
The current bootaux supports i.MX8M and i.MX93, but the name "_M4_" implies that the SoCs have Cortex-M4. Actually i.MX8MM/Q use Cortex-M4, i.MX8MN/P use Cortex-M7, i.MX93 use Cortex-M33, so use "_MCU_" in place of "_M4_" to simplify the naming. Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-12Merge tag v2023.07-rc4 into nextTom Rini1-1/+1
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-31imx: fix header inclusion guardsAndre Przywara1-1/+1
It seems like the header inclusion guards for some IMX related headers were misspelled or got out of sync. Make the preprocessor symbols for the #ifndef and #define lines the same, so that the double inclusion protection works as expected. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-05-21ddr: imx93: update the ddr init to support mult setpointsJacky Bai1-1/+1
Update the DDR init flow for multi-setpoint support on i.MX93. A new fsp_cfg struct need to be added in the timing file to store the diff part of the DDRC and DRAM MR register for each setpoint. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-30arm64: imx8mp: Drop EQoS GPR[1] board workaroundMarek Vasut1-1/+0
The EQoS interface mode is now configured in common board_interface_eth_init() and called by EQoS MAC driver when appropriate. Drop the board side duplicates if the same functionality. Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30net: fec_mxc: Add board_interface_eth_init() for i.MX8M Mini/Nano/PlusMarek Vasut1-0/+2
Implement common board_interface_eth_init() and call it from the FEC driver to configure IOMUXC GPR[1] register according to the PHY mode obtained from DT. This supports all three interface modes supported by the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side configuration of the same IOMUX GPR[1] duplicated in the board files. Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M PlusMarek Vasut1-1/+7
Implement common board_interface_eth_init() and call it from the DWMAC driver to configure IOMUXC GPR[1] register according to the PHY mode obtained from DT. This supports all three interface modes supported by the i.MX8M Plus DWMAC and supersedes current board-side configuration of the same IOMUX GPR[1] duplicated in the board files. Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31imx8mq_pins: fix configuration for UART4 on ECSPI2 padsArnaud Ferraris1-1/+1
When routing UART4 using the ECSPI2 pads, register IOMUXC_UART4_RXD_SELECT_INPUT (offset 0x050C) should be changed only when dealing with RX, as its name suggests. Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-31arm: imx: imx8m: Program CSU and TZASC if PSCI providerMarek Vasut1-0/+1
In case U-Boot is the PSCI provider, it is necessary to correctly program CSU and TZASC registers. Those are poorly documented, so push in the correct values. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: imx8m: Define trampoline location if PSCI providerMarek Vasut1-0/+4
The common code used to bring up secondary cores requires a final jump location to be stored in some sort of memory location, define this memory location to be the start of OCRAM, since it is available. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: imx8m: Enable GICv3 support if PSCI providerMarek Vasut1-0/+3
In case U-Boot is a PSCI provider, enable GICv3 support as this is necessary to bring up secondary cores. Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-14Merge tag 'u-boot-imx-20221114' of ↵Tom Rini1-1/+5
https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2022.01 ----------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083 - Fix UART - moved to binman (MX8 boards) - Toradex: sync DTS with Linux - Gateworks: fixes - New boards : MSC SM2S iMX8MP
2022-11-10global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespaceTom Rini1-6/+6
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-07ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MPMartyn Welch1-0/+4
The i.MX8MP SoC contains 2 more i2c buses. Add support for the configuration of these buses. Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-11-07imx8m: USDHC3 base address definition for i.MX8MPMartyn Welch1-1/+1
The i.MX8MP also has USDHC3, allow access to the relvant base address definition. Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-09-20ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlockMarek Vasut1-0/+5
Pull this LPGPR unlock into common code, since it is used in multiple systems already. Signed-off-by: Marek Vasut <marex@denx.de>
2022-08-12Convert CONFIG_SYS_FSL_MAX_NUM_OF_SEC to KconfigTom Rini1-1/+0
This converts the following to Kconfig: CONFIG_SYS_FSL_MAX_NUM_OF_SEC Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-26ddr: imx: Add i.MX9 DDR controller driverYe Li1-2/+4
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: move get_boot_device to common filePeng Fan1-0/+1
i.MX8MN/P/ULP supports ROM API, they have almost same get_boot_device implementation, so move to a common file. And when support i.MX9, no need to include the other function copy. Since sys_proto.h is included in imx_romapi.c, there will be build warning for i.MX8M because wdog_regs not defined, so include imx-regs.h in i.MX8M sys_proro.h Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: move get_boot_device to common headerPeng Fan1-1/+0
Most i.MX implements get_boot_device, move it to common header to simplify code Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-25configs: imx8mm: Define CONFIG_SYS_UBOOT_BASE for i.MX8mMamta Shukla1-0/+1
The macro `CONFIG_SYS_UBOOT_BASE` is used by SPL loaders `"NOR"` and `"XIP"` to determine the base address of u-boot. For `"NOR"` on i.MX8MM it is the base address of QSPI0 plus the offset of the flattened image tree blob. Although `QSPI0_AMBA_BASE` is used to define CONFIG_SYS_UBOOT_BASE in multiple board header files for i.MX8MM, it is not specified. Specify offset of flattened image tree blob (needs to be set to same value as specified in 'binman' node), base address of QSPI0 and size of FlexSPI configuration block. Signed-off-by: Mamta Shukla <mamta.shukla@leica-geosystems.com> Signed-off-by: Thomas Haemmerle <thomas.haemmerle@leica-geosystems.com> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2022-05-20imx8m: fix reading of DDR4 MR registersRasmus Villemoes1-0/+1
I was trying to employ lpddr4_mr_read() to something similar to what the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c differs from the private one used by that board in how it extracts the byte value, and I was only getting zeroes. Adding a bit of debug printf'ing gives me tmp = 0x00ffff00 tmp = 0x00070700 tmp = 0x00000000 tmp = 0x00101000 and indeed I was expecting a (combined) value of 0xff070010 (0xff being Manufacturer ID for Micron). I can't find any documentation that says how the values are supposed to be read, but clearly the iot-gate definition is the right one, both for its use case as well as my imx8mp-based board. So lift the private definition of lpddr4_mr_read() from the imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration in the ddr.h header where e.g. get_trained_CDD() is already declared. This has only been compile-tested for the imx8mm-cl-iot-gate board (since I don't have the hardware), but since I've merely moved its definition of lpddr4_mr_read(), I'd be surprised if it changed anything for that board. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20ARM: imx: imx8m: Introduce and use UART_BASE_ADDR(n)Marek Vasut1-0/+10
Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base address. Convert all board configurations to this new macro. This is the first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a clean up, no functional change. The new macro contains compile-time test to verify N is in suitable range. The test works such that it multiplies constant N by constant double-negation of size of a non-empty structure, i.e. it multiplies constant N by constant 1 in each successful compilation case. The non-empty structure may contain C11 _Static_assert(), make use of this and place the kernel variant of static assert in there, so that it performs the compile-time check for N in the correct range. Note that it is not possible to directly use static_assert in compound statements, hence this convoluted construct. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2022-04-21imx: power-domain: Inline arch-imx8m/power-domain.hMarek Vasut1-15/+0
The arch/arm/include/asm/arch-imx8m/power-domain.h is not included anywhere except in drivers/power/domain/imx8m-power-domain.c, just inline the content and drop the header. No functional change. Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-defconfig Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2022-04-12imx8m: add init_nand_clkMichael Trimarchi1-0/+1
Add init_nand_clk to enable gpmi nand clock. Since i.MX8M not use CCF, so we still use legacy mode to configure the clock. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-04-12imx8m: add regs used by GPMIMichael Trimarchi1-0/+7
Add regs used by GPMI Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-04-12arch: mach-imx: imx8m: add pwm_regs struct in imx-regsTommaso Merciai1-0/+9
Add pwm_regs struct for i.MX8MM SOC Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
2022-04-12arch: mach-imx: imx8m: add pwm ctrl registers fields definesTommaso Merciai1-0/+8
Add pwm control registers fields defines into imx-regs.h: - prescaler - dozeen - waiten - dbgen - clksrc_ipg_high - clksrc_ipg, en field References: - iMX8MMRM.pdf p 3884 Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
2022-02-05imx8m: lock id_swap_bypass bit in tzc380 enableAndrey Zhizhikin1-2/+4
According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in order to avoid AXI bus errors when GPU is enabled on the platform. TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable derivatives, but is missing a lock settings to be applied. Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have it implemented. Since we're here, provide also names to bits from TRM instead of using BIT() macro in the code. Fixes: deca6cfbf5d7 ("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors") Fixes: a07c7181296f ("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Peng Fan <peng.fan@nxp.com>
2021-07-17arm: imx8mq: Add USB clock init functionYe Li1-0/+1
Add clock function to setup relevant clocks for USB3.0 controllers and PHYs on i.MX8MQ Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se>
2021-04-08iMX8M: Add support to enable CONFIG_IMX_HABYe Li1-0/+1
Add some SOC level codes and build configurations to use HAB lib for CONFIG_IMX_HAB (secure boot), like adding the SEC_CONFIG fuse, enable fuse driver, CAAM clock function, and add CAAM secure RAM to MMU table. The FSL_CAAM is temporally not enabled for iMX8M when CONFIG_IMX_HAB is set, because we don't need the CAAM driver for SPL. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08imx8m: add regs used by CAAMPeng Fan1-0/+10
Add regs used by CAAM Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08arch: mach-imx: imx8m: fix unique_id read error for imx8mpPeng Fan1-0/+11
The value of Unique ID in uboot and kernel is different for iMX8MP: serial#=02e1444a0002aaff root@imx8mpevk:/sys/devices/soc0# cat soc_uid D699300002E1444A The reason is that Fuse Addresses of Unique ID of iMX8MP are 0x420 and 0x430. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-03-01ARM: imx: Add missing FEC ethernet quirk for MX8MMarek Vasut1-0/+1
The MX8M also contains a gigabit MAC, so define FEC_QUIRK_ENET_MAC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-01-23imx8m: clock: add type of set_clk_eqosPeng Fan1-0/+1
Add type of set_clk_eqos to make it could be used by other files. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-23imx: imx8mp_evk: enable eth supportPeng Fan1-0/+2
Add board code to configure the network interface Add net defconfig Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-12-13dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass1-1/+1
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-17imx8mq: fix SSCG_PLL_REFCLK_SEL_xPeng Fan1-4/+4
Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16 Reported-by: Coverity 3448860 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17imx8mq: fix FRAC_PLL_REFCLK_SEL_MASKPeng Fan1-1/+1
Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK was wrongly set. Reported-by: Coverity 10045172 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-07-14imx8m: power down fused coresPeng Fan1-0/+158
For non-Quad SoCs, the fused cpu cores could be powered down in SPL to save power. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issueOliver Chen1-0/+3
Add logic to automatically update umctl2's setting based on phy training CDD value for rank to rank space issue Acked-by: Ye Li <ye.li@nxp.com> Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14drivers: ddr: imx8mp: Add inline ECC feature supportSherry Sun1-0/+7
the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass2-0/+8
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10imx: regs: add more fuse bank structurePeng Fan1-7/+34
Add more fuse bank structure for use. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8mm: clock: fix fracpll decode issueYe Li1-1/+1
The fracpll decoding is using the bit definitions for int pll. Most of them are same, but the CLKE bit is different. Fix the wrong CLKE_MASK for fracpll and correct all bit definitions in fracpll decoding. Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8mq: Set ARM core clock directly from ARM PLLPeng Fan1-1/+2
For ARM core clock, there are two input branches, and can select via mux: one from ARM PLL directly, second from CCM A53 clock root. Currently we are using second branch. But IC confirmed the CCM A53 root signoff timing is 1Ghz, so we should switch to input from ARM PLL directly. This patch fixes the CORE SEL slice configuration and switch ARM clock to ARM PLL. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.1 at 2024-07-30 08:18:19 +0000