diff options
Diffstat (limited to 'arch/arm')
24 files changed, 162 insertions, 104 deletions
diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi new file mode 100644 index 0000000..322c858 --- /dev/null +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (c) 2019 Simon Goldschmidt + */ +/{ + soc { + u-boot,dm-pre-reloc; + }; +}; + +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 2458d67..51a6a51 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -84,6 +84,7 @@ #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; + resets = <&rst DMA_RESET>; }; }; @@ -100,6 +101,7 @@ reg = <0xffc00000 0x1000>; interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; clocks = <&can0_clk>; + resets = <&rst CAN0_RESET>; status = "disabled"; }; @@ -108,6 +110,7 @@ reg = <0xffc01000 0x1000>; interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; clocks = <&can1_clk>; + resets = <&rst CAN1_RESET>; status = "disabled"; }; @@ -585,6 +588,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff708000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO0_RESET>; status = "disabled"; porta: gpio-controller@0 { @@ -605,6 +609,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff709000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO1_RESET>; status = "disabled"; portb: gpio-controller@0 { @@ -625,6 +630,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff70a000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO2_RESET>; status = "disabled"; portc: gpio-controller@0 { @@ -735,6 +741,7 @@ #size-cells = <0>; clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; + resets = <&rst SDMMC_RESET>; status = "disabled"; }; @@ -746,9 +753,9 @@ <0xffb80000 0x10000>; reg-names = "nand_data", "denali_reg"; interrupts = <0x0 0x90 0x4>; - dma-mask = <0xffffffff>; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>; status = "disabled"; }; @@ -759,7 +766,7 @@ qspi: spi@ff705000 { compatible = "cdns,qspi-nor"; - #address-cells = <1>; + #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, <0xffa00000 0x1000>; @@ -768,6 +775,7 @@ cdns,fifo-width = <4>; cdns,trigger-address = <0x00000000>; clocks = <&qspi_clk>; + resets = <&rst QSPI_RESET>; status = "disabled"; }; @@ -783,9 +791,10 @@ reg = <0xfffec000 0x100>; }; - sdr: sdr@ffc25000 { + sdr: sdr@ffc20000 { compatible = "altr,sdr-ctl", "syscon"; - reg = <0xffc25000 0x1000>; + reg = <0xffc20000 0x6000>; + resets = <&rst SDR_RESET>; }; sdramedac { @@ -802,6 +811,7 @@ interrupts = <0 154 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM0_RESET>; status = "disabled"; }; @@ -813,6 +823,7 @@ interrupts = <0 155 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM1_RESET>; status = "disabled"; }; @@ -879,6 +890,7 @@ dmas = <&pdma 28>, <&pdma 29>; dma-names = "tx", "rx"; + resets = <&rst UART0_RESET>; }; uart1: serial1@ffc03000 { @@ -891,6 +903,7 @@ dmas = <&pdma 30>, <&pdma 31>; dma-names = "tx", "rx"; + resets = <&rst UART1_RESET>; }; usbphy0: usbphy { @@ -930,6 +943,7 @@ reg = <0xffd02000 0x1000>; interrupts = <0 171 4>; clocks = <&osc1>; + resets = <&rst L4WD0_RESET>; status = "disabled"; }; @@ -938,6 +952,7 @@ reg = <0xffd03000 0x1000>; interrupts = <0 172 4>; clocks = <&osc1>; + resets = <&rst L4WD1_RESET>; status = "disabled"; }; }; diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi index e75f290..dfaff4c 100644 --- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts index a387071..6439daa 100644 --- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts +++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts @@ -4,6 +4,7 @@ */ #include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" / { model = "Devboards.de DBM-SoC1"; @@ -24,10 +25,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi index 08d81da..0219c69 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi @@ -6,14 +6,12 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index e910574..b620dd8 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -6,6 +6,7 @@ */ #include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" / { model = "Terasic DE10-Nano"; @@ -26,10 +27,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts index 4f076bc..ff1e61e 100644 --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts @@ -4,6 +4,7 @@ */ #include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" / { model = "Terasic DE1-SoC"; @@ -24,10 +25,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index 93e4d45..2d31412 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -4,6 +4,7 @@ */ #include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" / { model = "SoCFPGA Cyclone V IS1"; @@ -31,10 +32,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi index 2fafd7e..7d9874c 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &can0 { diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi index 7ef3053..85cc396 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi index 1003115..0a4d54e 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 93c3fa4..8d5d399 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -76,7 +76,6 @@ &qspi { status = "okay"; - u-boot,dm-pre-reloc; flash: flash@0 { #address-cells = <1>; @@ -91,6 +90,5 @@ cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; status = "okay"; - u-boot,dm-pre-reloc; }; }; diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts index 1a18c4f..bb29da6 100644 --- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -4,6 +4,7 @@ */ #include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" / { model = "SoCFPGA Cyclone V SR1500"; @@ -27,10 +28,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index e05ca82..db55a4e 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb0; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &watchdog0 { diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ee93725..d1ae2fa 100644..100755 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -237,6 +237,19 @@ reg = <0xffe00000 0x100000>; }; + qspi: spi@ff8d2000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff8d2000 0x100>, + <0xff900000 0x100000>; + interrupts = <0 3 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + status = "disabled"; + }; + rst: rstmgr@ffd11000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi new file mode 100755 index 0000000..e1cfb52 --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +/{ + aliases { + spi0 = &qspi; + }; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index 6e8ddcd..2745050 100644..100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -36,7 +36,9 @@ memory { device_type = "memory"; - reg = <0 0 0 0x80000000>; /* 2GB */ + /* 4GB */ + reg = <0 0x00000000 0 0x80000000>, + <1 0x80000000 0 0x80000000>; u-boot,dm-pre-reloc; }; }; @@ -85,6 +87,41 @@ smplsel = <0>; }; +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00a"; + reg = <0>; + spi-max-frequency = <50000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x4000000>; + }; + + qspi_rootfs: partition@4000000 { + label = "Root Filesystem - JFFS2"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h index 31b73ed..e186296 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h @@ -9,6 +9,7 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +int cpu_has_been_warmreset(void); void socfpga_bridges_reset(int enable); @@ -47,6 +48,8 @@ struct socfpga_reset_manager { #define RSTMGR_MPUMODRST_CORE0 0 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 #define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 +/* Watchdogs and MPU warm reset mask */ +#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 /* * Define a reset identifier, from which a permodrst bank ID diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h index a238d5d..c412085 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h @@ -7,10 +7,6 @@ #ifndef __ASSEMBLY__ -unsigned long sdram_calculate_size(void); -int sdram_mmr_init_full(unsigned int sdr_phy_reg); -int sdram_calibration_full(void); - const struct socfpga_sdram_config *socfpga_get_sdram_config(void); void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h index ca68594..f39206c 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h @@ -22,6 +22,7 @@ int sdram_calibration_full(void); #define ECCCTRL1 0x100 #define ECCCTRL2 0x104 #define ERRINTEN 0x110 +#define ERRINTENS 0x114 #define INTMODE 0x11c #define INTSTAT 0x120 #define AUTOWB_CORRADDR 0x138 @@ -52,6 +53,10 @@ int sdram_calibration_full(void); #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f +#define DDR_HMC_ERRINTEN_INTMASK \ + (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ + DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK) + /* NOC DDR scheduler */ #define DDR_SCH_ID_COREID 0 #define DDR_SCH_ID_REVID 0x4 @@ -180,4 +185,8 @@ int sdram_calibration_full(void); #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ (((x) >> 0) & 0xFF) +/* Firewall DDR scheduler MPFE */ +#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 +#define FW_HMC_ADAPTOR_MPU_MASK BIT(0) + #endif /* _SDRAM_S10_H_ */ diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 6e11ba6..9865f5b 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -201,16 +201,6 @@ int arch_early_init_r(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(&altera_fpga[0]); -#ifdef CONFIG_DESIGNWARE_SPI - /* Get Designware SPI controller out of reset */ - socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); - socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); -#endif - -#ifdef CONFIG_NAND_DENALI - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); -#endif - return 0; } diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index f176c38..f8dd787 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -103,3 +103,12 @@ void reset_deassert_peripherals_handoff(void) writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst); writel(0, &reset_manager_base->per0modrst); } + +/* + * Return non-zero if the CPU has been warm reset + */ +int cpu_has_been_warmreset(void) +{ + return readl(&reset_manager_base->status) & + RSTMGR_L4WD_MPU_WARMRESET_MASK; +} diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 142b60f..9dd0afb 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -21,6 +21,7 @@ #include <debug_uart.h> #include <fdtdec.h> #include <watchdog.h> +#include <dm/uclass.h> DECLARE_GLOBAL_DATA_PTR; @@ -38,16 +39,12 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ case 0x3: /* NAND Flash (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); return BOOT_DEVICE_NAND; case 0x4: /* SD/MMC External Transceiver (1.8V) */ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); - socfpga_per_reset(SOCFPGA_RESET(DMA), 0); return BOOT_DEVICE_MMC1; case 0x6: /* QSPI Flash (1.8V) */ case 0x7: /* QSPI Flash (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); return BOOT_DEVICE_SPI; default: printf("Invalid boot device (bsel=%08x)!\n", bsel); @@ -123,9 +120,9 @@ static void socfpga_pl310_clear(void) void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); - unsigned long sdram_size; unsigned long reg; int ret; + struct udevice *dev; /* * First C code to run. Clear fake OCRAM ECC first as SBE @@ -156,10 +153,7 @@ void board_init_f(ulong dummy) socfpga_bridges_reset(1); } - socfpga_per_reset(SOCFPGA_RESET(SDR), 0); - socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); - timer_init(); debug("Reconfigure Clock Manager\n"); @@ -181,8 +175,7 @@ void board_init_f(ulong dummy) sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0); - /* De-assert reset for peripherals and bridges based on handoff */ - reset_deassert_peripherals_handoff(); + /* De-assert reset for bridges based on handoff */ socfpga_bridges_reset(0); debug("Unfreezing/Thaw all I/O banks\n"); @@ -200,27 +193,16 @@ void board_init_f(ulong dummy) hang(); } + ret = uclass_get_device(UCLASS_RESET, 0, &dev); + if (ret) + debug("Reset init failed: %d\n", ret); + /* enable console uart printing */ preloader_console_init(); - if (sdram_mmr_init_full(0xffffffff) != 0) { - puts("SDRAM init failed.\n"); - hang(); - } - - debug("SDRAM: Calibrating PHY\n"); - /* SDRAM calibration */ - if (sdram_calibration_full() == 0) { - puts("SDRAM calibration failed.\n"); - hang(); - } - - sdram_size = sdram_calculate_size(); - debug("SDRAM: %ld MiB\n", sdram_size >> 20); - - /* Sanity check ensure correct SDRAM size specified */ - if (get_ram_size(0, sdram_size) != sdram_size) { - puts("SDRAM size check failed!\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); hang(); } diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index a3db20a..a141ffe 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -181,17 +181,6 @@ void board_init_f(ulong dummy) hang(); } - gd->ram_size = sdram_calculate_size(); - printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20)); - - /* Sanity check ensure correct SDRAM size specified */ - debug("DDR: Running SDRAM size sanity check\n"); - if (get_ram_size(0, gd->ram_size) != gd->ram_size) { - puts("DDR: SDRAM size check failed!\n"); - hang(); - } - debug("DDR: SDRAM size check passed!\n"); - mbox_init(); #ifdef CONFIG_CADENCE_QSPI |