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| author | Jonas Karlman <jonas@kwiboo.se> | 2023-07-22 13:30:22 +0000 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-07-28 18:45:03 +0800 |
| commit | 583a82d5e2702f2c8aadcd75d416d6e45dd5188a (patch) | |
| tree | 563e021682fa57cafd219d0e18db0dcd795b957a /drivers/clk/rockchip | |
| parent | f7b8a84a29833b6e6ddac67920d688330b299fa8 (diff) | |
| download | u-boot-583a82d5e2702f2c8aadcd75d416d6e45dd5188a.zip u-boot-583a82d5e2702f2c8aadcd75d416d6e45dd5188a.tar.gz u-boot-583a82d5e2702f2c8aadcd75d416d6e45dd5188a.tar.bz2 | |
rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support
Add dummy support for the CLK_PCIEPHY2_REF clock.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3568.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 6bdd96f..0df82f5 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -427,6 +427,7 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) break; case CLK_PCIEPHY0_REF: case CLK_PCIEPHY1_REF: + case CLK_PCIEPHY2_REF: return 0; default: return -ENOENT; |