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author | wdenk <wdenk> | 2003-06-27 21:31:46 +0000 |
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committer | wdenk <wdenk> | 2003-06-27 21:31:46 +0000 |
commit | 8bde7f776c77b343aca29b8c7b58464d915ac245 (patch) | |
tree | 20f1fd99975215e7c658454a15cdb4ed4694e2d4 /cpu/mpc824x/drivers/epic/epic2.S | |
parent | 993cad9364c6b87ae429d1ed1130d8153f6f027e (diff) | |
download | u-boot-8bde7f776c77b343aca29b8c7b58464d915ac245.zip u-boot-8bde7f776c77b343aca29b8c7b58464d915ac245.tar.gz u-boot-8bde7f776c77b343aca29b8c7b58464d915ac245.tar.bz2 |
* Code cleanup:LABEL_2003_06_27_2340
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
Diffstat (limited to 'cpu/mpc824x/drivers/epic/epic2.S')
-rw-r--r-- | cpu/mpc824x/drivers/epic/epic2.S | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/cpu/mpc824x/drivers/epic/epic2.S b/cpu/mpc824x/drivers/epic/epic2.S index 8979f88..8cc2fc6 100644 --- a/cpu/mpc824x/drivers/epic/epic2.S +++ b/cpu/mpc824x/drivers/epic/epic2.S @@ -17,14 +17,14 @@ **********************************************/ .text .align 2 - .global CoreExtIntEnable + .global CoreExtIntEnable CoreExtIntEnable: - mfmsr r3 + mfmsr r3 - ori r3,r3,0x8000 /* enable external interrupt */ - mtmsr r3 + ori r3,r3,0x8000 /* enable external interrupt */ + mtmsr r3 - bclr 20, 0 + bclr 20, 0 /******************************************* * function: CoreExtIntDisable @@ -35,20 +35,20 @@ CoreExtIntEnable: *******************************************/ .text .align 2 - .global CoreExtIntDisable + .global CoreExtIntDisable CoreExtIntDisable: - mfmsr r4 + mfmsr r4 xor r3,r3,r3 or r3,r3,r4 andis. r4,r4,0xffff - andi. r3,r3,0x7fff /* disable external interrupt */ + andi. r3,r3,0x7fff /* disable external interrupt */ or r3,r3,r4 - mtmsr r3 + mtmsr r3 - bclr 20, 0 + bclr 20, 0 /********************************************************* * function: epicEOI @@ -61,20 +61,20 @@ CoreExtIntDisable: ********************************************************/ .text .align 2 - .global epicEOI + .global epicEOI epicEOI: lis r5,0x0006 /* Build End Of Interrupt Register offset */ ori r5,r5,0x00b0 xor r7,r7,r7 /* Clear r7 */ stwbrx r7,r5,r3 /* Save r7, writing to this register will - * intidate the end of processing the - * highest interrupt. - */ + * intidate the end of processing the + * highest interrupt. + */ sync /* ---RESTORE MACHINE STATE */ mfmsr r13 /* Clear Recoverable Interrupt bit in MSR */ - or r7,r7,r13 + or r7,r7,r13 andis. r7,r7,0xffff andi. r13,r13,0x7ffd /* (and disable interrupts) */ @@ -147,8 +147,8 @@ epic_exception: stw r3,0x1c(r1) /* Push CTR */ mtspr SPRG0,r1 /* Save updated Supervisor stack pointer - * value to SPRG0 - */ + * value to SPRG0 + */ mfmsr r3 ori r3,r3,0x0002 /* Set Recoverable Interrupt bit in MSR */ mtmsr r3 @@ -159,8 +159,8 @@ epic_exception: /* ---READ EPIC REGISTER: PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */ lis r5,0x0006 /* Build Interrupt Acknowledge Register - * offset - */ + * offset + */ ori r5,r5,0x00a0 lwbrx r7,r5,r6 /* Load interrupt vector into r7 */ sync |