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author | wdenk <wdenk> | 2003-06-27 21:31:46 +0000 |
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committer | wdenk <wdenk> | 2003-06-27 21:31:46 +0000 |
commit | 8bde7f776c77b343aca29b8c7b58464d915ac245 (patch) | |
tree | 20f1fd99975215e7c658454a15cdb4ed4694e2d4 /cpu/mpc824x/drivers/epic | |
parent | 993cad9364c6b87ae429d1ed1130d8153f6f027e (diff) | |
download | u-boot-8bde7f776c77b343aca29b8c7b58464d915ac245.zip u-boot-8bde7f776c77b343aca29b8c7b58464d915ac245.tar.gz u-boot-8bde7f776c77b343aca29b8c7b58464d915ac245.tar.bz2 |
* Code cleanup:LABEL_2003_06_27_2340
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
Diffstat (limited to 'cpu/mpc824x/drivers/epic')
-rw-r--r-- | cpu/mpc824x/drivers/epic/README | 2 | ||||
-rw-r--r-- | cpu/mpc824x/drivers/epic/epic.h | 8 | ||||
-rw-r--r-- | cpu/mpc824x/drivers/epic/epic1.c | 15 | ||||
-rw-r--r-- | cpu/mpc824x/drivers/epic/epic2.S | 38 | ||||
-rw-r--r-- | cpu/mpc824x/drivers/epic/epicutil.S | 11 |
5 files changed, 35 insertions, 39 deletions
diff --git a/cpu/mpc824x/drivers/epic/README b/cpu/mpc824x/drivers/epic/README index ae95b88..5798996 100644 --- a/cpu/mpc824x/drivers/epic/README +++ b/cpu/mpc824x/drivers/epic/README @@ -100,5 +100,3 @@ USAGE: shall always call the epicEOI just before rfi instruction. Refer to the routine, epic_exception, for a code sample. - - diff --git a/cpu/mpc824x/drivers/epic/epic.h b/cpu/mpc824x/drivers/epic/epic.h index 17e4afb..58f81c5 100644 --- a/cpu/mpc824x/drivers/epic/epic.h +++ b/cpu/mpc824x/drivers/epic/epic.h @@ -123,7 +123,7 @@ void epicVendorId( unsigned int *step, unsigned int *venId ); void epicFeatures( unsigned int *noIRQs, - unsigned int *noCPUs, + unsigned int *noCPUs, unsigned int *VerId ); extern void epicInit( unsigned int IRQType, unsigned int clkRatio); ULONG sysEUMBBARRead ( ULONG regNum ); @@ -131,8 +131,8 @@ void sysEUMBBARWrite ( ULONG regNum, ULONG regVal); extern void epicTmFrequencySet( unsigned int frq ); extern unsigned int epicTmFrequencyGet(void); extern unsigned int epicTmBaseSet( ULONG srcAddr, - unsigned int cnt, - unsigned int inhibit ); + unsigned int cnt, + unsigned int inhibit ); extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val ); extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ); extern unsigned int epicTmInhibit( unsigned int timer ); @@ -144,7 +144,7 @@ extern void epicIntTaskSet( unsigned char val ); extern unsigned int epicIntAck(void); extern void epicSprSet( unsigned int eumbbar, unsigned char ); extern void epicConfigGet( unsigned int *clkRatio, - unsigned int *serEnable ); + unsigned int *serEnable ); extern void SrcVecTableInit(void); extern unsigned int epicModeGet(void); extern void epicIntEnable(int Vect); diff --git a/cpu/mpc824x/drivers/epic/epic1.c b/cpu/mpc824x/drivers/epic/epic1.c index eb7ed40..f89deed 100644 --- a/cpu/mpc824x/drivers/epic/epic1.c +++ b/cpu/mpc824x/drivers/epic/epic1.c @@ -78,12 +78,12 @@ void epicInit tmp = sysEUMBBARRead(EPIC_INT_CONF_REG); /* Read interrupt conf. reg */ if (IRQType == EPIC_DIRECT_IRQ) /* direct mode */ - sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff); + sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff); else /* Serial mode */ - { - tmp = (clkRatio << 28) | 0x08000000; /* Set clock ratio */ - sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp); - } + { + tmp = (clkRatio << 28) | 0x08000000; /* Set clock ratio */ + sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp); + } while (epicIntAck() != 0xff) /* Clear all pending interrupts */ epicEOI(); @@ -168,7 +168,7 @@ int epicIntSourceConfig tmp = sysEUMBBARRead(srAddr); actBit = (tmp & 40000000) >> 30; /* retrieve activity bit - bit 30 */ if (actBit == 1) - return ERROR; + return ERROR; tmp &= 0xff30ff00; /* Erase previously set P,S,Prio,Vector bits */ newVal = (Polarity << 23) | (Sense << 22) | (Prio << 16) | Vect; @@ -220,7 +220,7 @@ int epicCurTaskPrioSet { if ( (prioNum < 0) || (prioNum > 0xF)) - return ERROR; + return ERROR; sysEUMBBARWrite(EPIC_PROC_CTASK_PRI_REG, prioNum); return OK; } @@ -465,7 +465,6 @@ unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ) } - /*********************************************************** * function: epicTmInhibit * diff --git a/cpu/mpc824x/drivers/epic/epic2.S b/cpu/mpc824x/drivers/epic/epic2.S index 8979f88..8cc2fc6 100644 --- a/cpu/mpc824x/drivers/epic/epic2.S +++ b/cpu/mpc824x/drivers/epic/epic2.S @@ -17,14 +17,14 @@ **********************************************/ .text .align 2 - .global CoreExtIntEnable + .global CoreExtIntEnable CoreExtIntEnable: - mfmsr r3 + mfmsr r3 - ori r3,r3,0x8000 /* enable external interrupt */ - mtmsr r3 + ori r3,r3,0x8000 /* enable external interrupt */ + mtmsr r3 - bclr 20, 0 + bclr 20, 0 /******************************************* * function: CoreExtIntDisable @@ -35,20 +35,20 @@ CoreExtIntEnable: *******************************************/ .text .align 2 - .global CoreExtIntDisable + .global CoreExtIntDisable CoreExtIntDisable: - mfmsr r4 + mfmsr r4 xor r3,r3,r3 or r3,r3,r4 andis. r4,r4,0xffff - andi. r3,r3,0x7fff /* disable external interrupt */ + andi. r3,r3,0x7fff /* disable external interrupt */ or r3,r3,r4 - mtmsr r3 + mtmsr r3 - bclr 20, 0 + bclr 20, 0 /********************************************************* * function: epicEOI @@ -61,20 +61,20 @@ CoreExtIntDisable: ********************************************************/ .text .align 2 - .global epicEOI + .global epicEOI epicEOI: lis r5,0x0006 /* Build End Of Interrupt Register offset */ ori r5,r5,0x00b0 xor r7,r7,r7 /* Clear r7 */ stwbrx r7,r5,r3 /* Save r7, writing to this register will - * intidate the end of processing the - * highest interrupt. - */ + * intidate the end of processing the + * highest interrupt. + */ sync /* ---RESTORE MACHINE STATE */ mfmsr r13 /* Clear Recoverable Interrupt bit in MSR */ - or r7,r7,r13 + or r7,r7,r13 andis. r7,r7,0xffff andi. r13,r13,0x7ffd /* (and disable interrupts) */ @@ -147,8 +147,8 @@ epic_exception: stw r3,0x1c(r1) /* Push CTR */ mtspr SPRG0,r1 /* Save updated Supervisor stack pointer - * value to SPRG0 - */ + * value to SPRG0 + */ mfmsr r3 ori r3,r3,0x0002 /* Set Recoverable Interrupt bit in MSR */ mtmsr r3 @@ -159,8 +159,8 @@ epic_exception: /* ---READ EPIC REGISTER: PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */ lis r5,0x0006 /* Build Interrupt Acknowledge Register - * offset - */ + * offset + */ ori r5,r5,0x00a0 lwbrx r7,r5,r6 /* Load interrupt vector into r7 */ sync diff --git a/cpu/mpc824x/drivers/epic/epicutil.S b/cpu/mpc824x/drivers/epic/epicutil.S index a83fbd8..4877050 100644 --- a/cpu/mpc824x/drivers/epic/epicutil.S +++ b/cpu/mpc824x/drivers/epic/epicutil.S @@ -29,12 +29,12 @@ load_runtime_reg: xor r5,r5,r5 - or r5,r5,r3 /* save eumbbar */ + or r5,r5,r3 /* save eumbbar */ lwbrx r3,r4,r5 sync - bclr 20, 0 + bclr 20, 0 /**************************************************************** * function: store_runtime_reg @@ -44,9 +44,9 @@ load_runtime_reg: * r5 - new value to be stored * ****************************************************************/ - .text - .align 2 - .global store_runtime_reg + .text + .align 2 + .global store_runtime_reg store_runtime_reg: xor r0,r0,r0 @@ -55,4 +55,3 @@ store_runtime_reg: sync bclr 20,0 - |