diff options
author | Tom Rini <trini@konsulko.com> | 2020-05-25 14:09:42 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2020-05-25 14:09:42 -0400 |
commit | 60c7facfc965af6ff8ea14ee26c9d49cd2d0ec22 (patch) | |
tree | 7bc7f20aae283028bca5fde34205e3ab7fc618de /arch | |
parent | 71f70cfcf4a79a58682596e6b7769fe6f8f0c4d1 (diff) | |
parent | c02712a7484918648e5dd09c092035c7eeb7794a (diff) | |
download | u-boot-60c7facfc965af6ff8ea14ee26c9d49cd2d0ec22.zip u-boot-60c7facfc965af6ff8ea14ee26c9d49cd2d0ec22.tar.gz u-boot-60c7facfc965af6ff8ea14ee26c9d49cd2d0ec22.tar.bz2 |
Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Enable DM_ETH on omap3_logic board
- Enable Caches in SPL for K3 platforms
- Enable backup boot mode support for J721E
- Update the DDR timings for AM654 EVM
- Add automated tests for RX-51
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi | 28 | ||||
-rw-r--r-- | arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi | 10 | ||||
-rw-r--r-- | arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi | 10 | ||||
-rw-r--r-- | arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi | 10 | ||||
-rw-r--r-- | arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi | 12 | ||||
-rw-r--r-- | arch/arm/mach-k3/am6_init.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-k3/common.c | 35 | ||||
-rw-r--r-- | arch/arm/mach-k3/common.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-k3/include/mach/j721e_hardware.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-k3/include/mach/j721e_spl.h | 12 | ||||
-rw-r--r-- | arch/arm/mach-k3/j721e_init.c | 36 |
11 files changed, 141 insertions, 16 deletions
diff --git a/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi index d07aaea..5638321 100644 --- a/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by AM65x_DRA80xM_EMIF_Tool_1.98.xlsm + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated by AM65x_DRA80xM_EMIF_Tool_2.02.xlsm * http://www.ti.com/lit/pdf/spracj0 * Configuration Parameters * Memory Type: DDR4 @@ -24,7 +24,7 @@ #define DDRCTL_INIT4 0x00000020 #define DDRCTL_INIT5 0x00100000 #define DDRCTL_INIT6 0x00000480 -#define DDRCTL_INIT7 0x000004E8 +#define DDRCTL_INIT7 0x00000497 #define DDRCTL_DRAMTMG0 0x0C0A1B0D #define DDRCTL_DRAMTMG1 0x00030313 #define DDRCTL_DRAMTMG2 0x0506050A @@ -33,10 +33,10 @@ #define DDRCTL_DRAMTMG5 0x04040302 #define DDRCTL_DRAMTMG6 0x00000004 #define DDRCTL_DRAMTMG7 0x00000404 -#define DDRCTL_DRAMTMG8 0x03030A05 +#define DDRCTL_DRAMTMG8 0x03030C05 #define DDRCTL_DRAMTMG9 0x00020208 #define DDRCTL_DRAMTMG10 0x001C180A -#define DDRCTL_DRAMTMG11 0x0E06010E +#define DDRCTL_DRAMTMG11 0x1106010E #define DDRCTL_DRAMTMG12 0x00020008 #define DDRCTL_DRAMTMG13 0x0B100002 #define DDRCTL_DRAMTMG14 0x00000000 @@ -84,33 +84,33 @@ #define DDRPHY_DCR 0x0000040C #define DDRPHY_DTPR0 0x041A0B06 #define DDRPHY_DTPR1 0x28140000 -#define DDRPHY_DTPR2 0x0034E255 -#define DDRPHY_DTPR3 0x01D50800 +#define DDRPHY_DTPR2 0x0034E300 +#define DDRPHY_DTPR3 0x02800800 #define DDRPHY_DTPR4 0x31180805 #define DDRPHY_DTPR5 0x00250B06 #define DDRPHY_DTPR6 0x00000505 #define DDRPHY_ZQCR 0x008A2A58 #define DDRPHY_ZQ0PR0 0x000077DD -#define DDRPHY_ZQ1PR0 0x000077DD +#define DDRPHY_ZQ1PR0 0x00007799 #define DDRPHY_MR0 0x00000214 #define DDRPHY_MR1 0x00000501 #define DDRPHY_MR2 0x00000000 #define DDRPHY_MR3 0x00000020 #define DDRPHY_MR4 0x00000000 #define DDRPHY_MR5 0x00000480 -#define DDRPHY_MR6 0x000004E8 +#define DDRPHY_MR6 0x00000497 #define DDRPHY_MR11 0x00000000 #define DDRPHY_MR12 0x00000000 #define DDRPHY_MR13 0x00000000 #define DDRPHY_MR14 0x00000000 #define DDRPHY_MR22 0x00000000 -#define DDRPHY_VTCR0 0xF3C32028 +#define DDRPHY_VTCR0 0xF3C32017 #define DDRPHY_DX8SL0PLLCR0 0x021c4000 #define DDRPHY_DX8SL1PLLCR0 0x021c4000 #define DDRPHY_DX8SL2PLLCR0 0x021c4000 #define DDRPHY_DTCR0 0x8000B1C7 #define DDRPHY_DTCR1 0x00010236 -#define DDRPHY_ACIOCR0 0x30070000 +#define DDRPHY_ACIOCR0 0xF0070000 #define DDRPHY_ACIOCR3 0x00000001 #define DDRPHY_ACIOCR5 0x04800000 #define DDRPHY_IOVCR0 0x0F0C0C0C @@ -157,6 +157,6 @@ #define DDRPHY_DX8SL0DXCTL2 0x00141830 #define DDRPHY_DX8SL1DXCTL2 0x00141830 #define DDRPHY_DX8SL2DXCTL2 0x00141830 -#define DDRPHY_DX8SL0DQSCTL 0x01264000 -#define DDRPHY_DX8SL1DQSCTL 0x01264000 -#define DDRPHY_DX8SL2DQSCTL 0x01264000 +#define DDRPHY_DX8SL0DQSCTL 0x01264300 +#define DDRPHY_DX8SL1DQSCTL 0x01264300 +#define DDRPHY_DX8SL2DQSCTL 0x01264300 diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi index 173b492..7832c9a 100644 --- a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi @@ -15,6 +15,16 @@ /delete-property/ serial1; /delete-property/ serial2; }; + + ethernet@08000000 { + compatible = "smsc,lan9221","smsc,lan9115"; + reg = <0x08000000 0xff>; + bank-width = <2>; + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; }; &gpio1 { diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi index 173b492..7832c9a 100644 --- a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi @@ -15,6 +15,16 @@ /delete-property/ serial1; /delete-property/ serial2; }; + + ethernet@08000000 { + compatible = "smsc,lan9221","smsc,lan9115"; + reg = <0x08000000 0xff>; + bank-width = <2>; + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; }; &gpio1 { diff --git a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi index 581247d..89b20be 100644 --- a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi @@ -15,6 +15,16 @@ /delete-property/ serial1; /delete-property/ serial2; }; + + ethernet@08000000 { + compatible = "smsc,lan9221","smsc,lan9115"; + reg = <0x08000000 0xff>; + bank-width = <2>; + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; }; &gpio1 { diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi index 9b709c1..e56666e 100644 --- a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi @@ -11,6 +11,18 @@ /delete-property/ serial1; /delete-property/ serial2; }; + + ethernet@08000000 { + compatible = "smsc,lan9221","smsc,lan9115"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x08000000 0xff>; + bank-width = <2>; + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; }; &i2c1 { diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index ddc9f3c..516a02e 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -198,6 +198,7 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif + spl_enable_dcache(); } u32 spl_mmc_boot_mode(const u32 boot_device) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 0cd34ac..9695b22 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -410,3 +410,38 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) } } } + +void spl_enable_dcache(void) +{ +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) + phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; + + dram_init_banksize(); + + /* reserve TLB table */ + gd->arch.tlb_size = PGTABLE_SIZE; + + ram_top += get_effective_memsize(); + /* keep ram_top in the 32-bit address space */ + if (ram_top >= 0x100000000) + ram_top = (phys_addr_t) 0x100000000; + + gd->arch.tlb_addr = ram_top - gd->arch.tlb_size; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + dcache_enable(); +#endif +} + +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); +} + +void spl_board_prepare_for_boot_linux(void) +{ + dcache_disable(); +} +#endif diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 57682e1..94cdcb5 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -27,3 +27,4 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size); void start_non_linux_remote_cores(void); int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr); void k3_sysfw_print_ver(void); +void spl_enable_dcache(void); diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h index 0deed66..19873d6 100644 --- a/arch/arm/mach-k3/include/mach/j721e_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -21,6 +21,8 @@ #define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1 #define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6) #define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6 +#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) +#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7 #define WKUP_CTRL_MMR0_BASE 0x43000000 #define MCU_CTRL_MMR0_BASE 0x40f00000 diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h index 959bdd4..3fa85ca 100644 --- a/arch/arm/mach-k3/include/mach/j721e_spl.h +++ b/arch/arm/mach-k3/include/mach/j721e_spl.h @@ -26,7 +26,19 @@ #define BOOT_DEVICE_MMC2_2 0x16 #define BOOT_DEVICE_RAM 0x17 +/* Backup boot modes with MCU Only = 0 */ +#define BACKUP_BOOT_DEVICE_RAM 0x0 +#define BACKUP_BOOT_DEVICE_USB 0x1 +#define BACKUP_BOOT_DEVICE_UART 0x3 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x4 +#define BACKUP_BOOT_DEVICE_MMC2 0x5 +#define BACKUP_BOOT_DEVICE_SPI 0x6 +#define BACKUP_BOOT_DEVICE_I2C 0x7 + #define BOOT_MODE_B_SHIFT 4 #define BOOT_MODE_B_MASK BIT(4) +#define K3_PRIMARY_BOOTMODE 0x0 +#define K3_BACKUP_BOOTMODE 0x1 + #endif diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 7a999f9..f9454e3 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -222,6 +222,7 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif + spl_enable_dcache(); } u32 spl_mmc_boot_mode(const u32 boot_device) @@ -236,6 +237,35 @@ u32 spl_mmc_boot_mode(const u32 boot_device) } } +static u32 __get_backup_bootmedia(u32 main_devstat) +{ + u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT; + + switch (bkup_boot) { + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_DFU; + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + case BACKUP_BOOT_DEVICE_MMC2: + { + u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >> + MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT; + if (port == 0x0) + return BOOT_DEVICE_MMC1; + return BOOT_DEVICE_MMC2; + } + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + } + + return BOOT_DEVICE_RAM; +} + static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat) { @@ -272,8 +302,10 @@ u32 spl_boot_device(void) /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */ main_devstat = readl(CTRLMMR_MAIN_DEVSTAT); - /* ToDo: Add support for backup boot media */ - return __get_primary_bootmedia(main_devstat, wkup_devstat); + if (bootindex == K3_PRIMARY_BOOTMODE) + return __get_primary_bootmedia(main_devstat, wkup_devstat); + else + return __get_backup_bootmedia(main_devstat); } #endif |