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| author | Rick Chen <rick@andestech.com> | 2019-04-30 13:49:33 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-05-09 16:46:46 +0800 |
| commit | bdce38965e79143ed58bf1c6d39c650ff3dfefd1 (patch) | |
| tree | dfb6c4288f22c176838ace87fed0949dd747a7dc /arch/riscv/cpu/cpu.c | |
| parent | 8aa278df0a338dfc05c731589051ab80373925c5 (diff) | |
| download | u-boot-bdce38965e79143ed58bf1c6d39c650ff3dfefd1.zip u-boot-bdce38965e79143ed58bf1c6d39c650ff3dfefd1.tar.gz u-boot-bdce38965e79143ed58bf1c6d39c650ff3dfefd1.tar.bz2 | |
riscv: Introduce CONFIG_XIP to support booting from flash
When U-Boot boots from flash, during the boot process,
hart_lottery and available_harts_lock variable addresses
point to flash which is not writable. This causes boot
failures on AE350. Introduce a config option CONFIG_XIP
to support such configuration.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/cpu/cpu.c')
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c32de8a..0cfd7d6 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -16,6 +16,7 @@ * before the bss section is available. */ phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; /* @@ -23,6 +24,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0; * finished initialization of global data. */ u32 available_harts_lock = 1; +#endif static inline bool supports_extension(char ext) { |