m68k: add basic set of devicetrees

This patch adds a basic group of devicetrees, one for each
cpu family, including actually just uart and dspi devices,
since these are the drivers supporting devicetree (support
added in this patch-set).

Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

18 files changed, 763 insertions, 0 deletions

diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi
new file mode 100644
index 0000000..558d8bf
--- /dev/null
+++ b/arch/m68k/dts/mcf5208.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5208";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5227x.dtsi b/arch/m68k/dts/mcf5227x.dtsi
new file mode 100644
index 0000000..8c95edd
--- /dev/null
+++ b/arch/m68k/dts/mcf5227x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5227x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi@fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi
new file mode 100644
index 0000000..9e79d47
--- /dev/null
+++ b/arch/m68k/dts/mcf523x.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf523x";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart@280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5249.dtsi b/arch/m68k/dts/mcf5249.dtsi
new file mode 100644
index 0000000..248b3dc
--- /dev/null
+++ b/arch/m68k/dts/mcf5249.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5249";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mbar: mbar@10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart@1c0 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x1c0 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5253.dtsi b/arch/m68k/dts/mcf5253.dtsi
new file mode 100644
index 0000000..3bde2d6
--- /dev/null
+++ b/arch/m68k/dts/mcf5253.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5253";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mbar: mbar@10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart@1c0 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x1c0 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart3: uart@c00 {
+				compatible = "fsl,mcf-uart";
+				reg = <0xc00 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi
new file mode 100644
index 0000000..2935552
--- /dev/null
+++ b/arch/m68k/dts/mcf5271.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5271";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart@280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5272.dtsi b/arch/m68k/dts/mcf5272.dtsi
new file mode 100644
index 0000000..a561177
--- /dev/null
+++ b/arch/m68k/dts/mcf5272.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5272";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mbar: mbar@10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart@100 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x100 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@140 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x140 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi
new file mode 100644
index 0000000..b375609
--- /dev/null
+++ b/arch/m68k/dts/mcf5275.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5275";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart@280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi
new file mode 100644
index 0000000..3ad1be7
--- /dev/null
+++ b/arch/m68k/dts/mcf5282.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5282";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ipsbar: ipsbar@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x40000000 0x40000000>;
+			reg = <0x40000000 0x40000000>;
+
+			uart0: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@240 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x240 0x40>;
+				status = "disabled";
+			};
+
+			uart2: uart@280 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x280 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5301x.dtsi b/arch/m68k/dts/mcf5301x.dtsi
new file mode 100644
index 0000000..0891e4d
--- /dev/null
+++ b/arch/m68k/dts/mcf5301x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5301x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi@fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5307.dtsi b/arch/m68k/dts/mcf5307.dtsi
new file mode 100644
index 0000000..e199cf9
--- /dev/null
+++ b/arch/m68k/dts/mcf5307.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5307";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* MBAR */
+		mbar: mbar@10000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x10000000 0x10000>;
+			reg = <0x10000000 0x10000>;
+
+			uart0: uart@1c0 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x1c0 0x40>;
+				status = "disabled";
+			};
+
+			uart1: uart@200 {
+				compatible = "fsl,mcf-uart";
+				reg = <0x200 0x40>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi
new file mode 100644
index 0000000..aeaa643
--- /dev/null
+++ b/arch/m68k/dts/mcf5329.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5329";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf537x.dtsi b/arch/m68k/dts/mcf537x.dtsi
new file mode 100644
index 0000000..aeaa643
--- /dev/null
+++ b/arch/m68k/dts/mcf537x.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5329";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi
new file mode 100644
index 0000000..71b392a
--- /dev/null
+++ b/arch/m68k/dts/mcf5441x.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5441x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		uart3: uart@fc06c000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc06c000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi@fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+
+		dspi1: dspi@fc03c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc03c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+
+		dspi2: dspi@ec038000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xec038000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+
+		dspi3: dspi@ec03c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xec03c00 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi
new file mode 100644
index 0000000..ccbee29
--- /dev/null
+++ b/arch/m68k/dts/mcf5445x.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf5445x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: uart@fc060000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc060000 0x40>;
+			status = "disabled";
+		};
+
+		uart1: uart@fc064000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc064000 0x40>;
+			status = "disabled";
+		};
+
+		uart2: uart@fc068000 {
+			compatible = "fsl,mcf-uart";
+			reg = <0xfc068000 0x40>;
+			status = "disabled";
+		};
+
+		dspi0: dspi@fc05c000 {
+			compatible = "fsl,mcf-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfc05c000 0x100>;
+			spi-max-frequency = <50000000>;
+			num-cs = <4>;
+			spi-mode = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/m68k/dts/mcf54xx.dtsi b/arch/m68k/dts/mcf54xx.dtsi
new file mode 100644
index 0000000..537bb42
--- /dev/null
+++ b/arch/m68k/dts/mcf54xx.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+	compatible = "fsl,mcf54x5";
+
+	aliases {
+		/* TO DO, clarify on serial, this SoC seems to have SPC and
+		 * no UARTS.
+		 */
+		spi0 = &dspi0;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mbar: mbar@80000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x80000000 0x10000>;
+			reg = <0x80000000 0x10000>;
+
+			dspi0: dspi@8a00 {
+				compatible = "fsl,mcf-dspi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x8a00 0x100>;
+				spi-max-frequency = <50000000>;
+				num-cs = <4>;
+				spi-mode = <0>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/doc/device-tree-bindings/serial/mcf-uart.txt b/doc/device-tree-bindings/serial/mcf-uart.txt
new file mode 100644
index 0000000..d73f764
--- /dev/null
+++ b/doc/device-tree-bindings/serial/mcf-uart.txt
@@ -0,0 +1,19 @@
+Freescale ColdFire UART
+
+Required properties:
+- compatible : should be "fsl,mcf-uart"
+- reg: start address and size of the registers
+
+Example:
+
+soc {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	uart0: uart@fc060000 {
+		compatible = "fsl,mcf-uart";
+		reg = <0xfc060000 0x40>;
+		status = "disabled";
+	};
+};
diff --git a/doc/device-tree-bindings/spi/spi-mcf-dspi.txt b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt
new file mode 100644
index 0000000..860eb8a
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt
@@ -0,0 +1,30 @@
+Freescale ColdFire DSPI controller
+
+Required properties:
+- compatible : "fsl,mcf-dspi"
+- #address-cells: <1>, as required by generic SPI binding
+- #size-cells: <0>, also as required by generic SPI binding
+- reg : offset and length of the register set for the device
+
+Optional properties:
+- spi-max-frequency : max supported spi frequency
+- num-cs : the number of the chipselect signals
+- spi-mode: spi motorola mode, 0 to 3
+- ctar-params: CTAR0 to 7 register configuration, as an array
+  of 8 integer fields for each register, where each register
+  is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>.
+
+Example:
+
+dspi0: dspi@fc05c000 {
+	compatible = "fsl,mcf-dspi";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0xfc05c000 0x100>;
+	spi-max-frequency = <50000000>;
+	num-cs = <4>;
+	spi-mode = <0>;
+	ctar-fields = <7, 0, 0, 0, 0, 0, 1, 6>,
+		      <7, 0, 0, 0, 0, 0, 1, 6>,
+		      <7, 0, 0, 0, 0, 0, 1, 6>;
+};