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2024-06-18lib: sbi: Add support for Svade and Svadu extensionsYong-Xuan Wang1-0/+12
Add support for Svade and Svadu extensions. When both are present in the device tree, the M-mode firmware should select the Svade extension to comply with the RVA23 profile, which mandates Svade and lists Svadu as an optional extension. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-05-07lib: sbi: Refine the settings for switching to Virtual Supervisor Mode.Pope B.Lei1-4/+11
Although Mstatus.MPV is set, before executing mret, access to VS mode registers should use the actual register addresses, not the pseudonyms of S registers. Signed-off-by: Pope B.Lei <popeblei@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-04-10lib: sbi: Add missing sscrind and sscfg extensions in sbi_hart_ext[]Clément Léger1-0/+5
The sbi_hart_ext[] array is missing these two extensions ids. It is expected that this array contains all the extensions declaration at the same index of the SBI_HART_EXT_* define. Without this, when adding a new extension, there is a mismatch between ids and extension names and it can even display corrupted extension names. Addresses-Coverity-ID: 1584994 Out-of-bounds read Fixes: 6bb6b61c27eb ("lib: sbi: Add support for smcsrind and smcdeleg") Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-03-04lib: sbi: Add support for smcsrind and smcdelegAtish Patra1-4/+12
Smcsrind allows generic indirect CSR access mechanism while Smcdeleg allows delegating hpmcounters in Supervisor mode. Enable both extensions and set the appropriate bits in mstateen and menvcfg. Co-developed-by: Kaiwen Xue <kaiwenxue1@gmail.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2024-01-10lib: sbi: Detect support of debug triggersHimanshu Chauhan1-0/+4
Detect if debug triggers, sdtrig extension, is supported by the CPU. The support is detected by access traps and ISA string parsing. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-12-27lib: sbi: Detect Zicntr extension only based on trapsAnup Patel1-0/+8
OpenSBI uses time CSR if Zicntr extension present which causes it to crash on an older QEMU because QEMU generates Zicntr in the ISA string for unleashed machine which only has CYCLE and INSTRET counters. Fixes: 776770d2adbf ("lib: sbi: Using one array to define the name of extensions") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-19lib: sbi: Do not enter OpenSBI with mseccfg.MML == 1Anup Patel1-0/+10
On platforms with Smepmp, the previous booting stage must enter OpenSBI with mseccfg.MML == 0. This allows OpenSBI to configure it's own M-mode only regions without depending on the previous booting stage. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2023-12-19lib: sbi: Detect extensions from the ISA string in DTYong-Xuan Wang1-34/+15
Enable access to some extensions through menvcfg and show them in "Boot HART ISA Extensions" if they are present in the device tree. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-12-19lib: sbi: Using one array to define the name of extensionsYong-Xuan Wang1-48/+20
Define an array sbi_hart_ext to map extension ID and name , and use it for ISA parsing and printing out the supported extensions. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-12-19lib: sbi: Refactor the code for enable extensions in menvfg CSRYong-Xuan Wang1-11/+9
Use 1 variable to store the value of menvcfg. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-12-19lib: sbi: Improve the code of privilege mode and extensions detectionYong-Xuan Wang1-50/+38
We can enhance the code by creating 2 unified interface with macro for privilege mode and extensions detection, which relies on supported privilege modes and CSRs. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-12-08lib: sbi_hart: Store PMP granularity as log base 2Samuel Holland1-15/+15
This minimizes the need to call log2roundup() to recover the log value. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-12-06lib: sbi: Add XAndesPMU in hart extensionsYu Chien Peter Lin1-0/+3
Add the custom extension to hart extension list. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-11-22lib: sbi: Fix PMP granularity handling in sbi_hart_map_saddr()Anup Patel1-1/+2
The sbi_hart_map_saddr() must create PMP mapping of size greater than or equal to PMP granularity otherwise PMP mapping does not work when size parameter less than sbi_hart_pmp_granularity(scratch). Fixes: 6e44ef686a9b ("lib: sbi: Add functions to map/unmap shared memory") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
2023-11-17lib: sbi: change sbi_hart_features.extensions as an arrayXiang W1-20/+12
In the future there may be a lot of ISA extensions, a 'long' may not be able to accommodate, changed to an array for the future. Addresses-Coverity-ID: 1568357 Out-of-bounds access Fixes: 6259b2ec2d09 ("lib: utils/fdt: Fix fdt_parse_isa_extensions() implementation") Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-11-17lib: sbi: enable seed access in S-modeHeinrich Schuchardt1-0/+6
If ISA extension Zkr is available, set mseccfg.sseed=1 mseccfg.useed=0 This enables access to the seed CSR in S-mode but not in U-mode. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-11-17lib: sbi: Add Zkr in hart extensionsHeinrich Schuchardt1-0/+3
- Add Zkr as extension in sbi_hart_extensions enum - Return "zkr" string for Zkr extension from sbi_hart_extension_id2string Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-09-24lib: sbi: Populate M-only Smepmp entries before setting mseccfg.MMLAnup Patel1-14/+59
Based on sections 4.c and 4.d in Ch.2 of the Smepmp spec the PMP entries must be programmed as below: 1. Program M-only entries 2. Enable mseccfg.MML 3. Program shared-region entries 4. Program SU-only entries Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2023-09-24lib: sbi: Fix pmp_flags for Smepmp read-only shared regionAnup Patel1-1/+1
The Smepmp read-only shared region must have pmpcfg.L, pmpcfg.R, pmpcfg.W, and pmpcfg.X bits set so sbi_hart_get_smepmp_flags() must return pmp_flags accordingly. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
2023-09-24lib: sbi: Don't clear mseccfg.MML bit in sbi_hart_smepmp_configure()Anup Patel1-4/+2
The mseccfg.MML bit is a sticky bit which remains unchanged once set so no need to clear it in sbi_hart_smepmp_configure(). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
2023-09-24lib: sbi: Factor-out Smepmp configuration as separate functionAnup Patel1-70/+110
Let us factor-out Smepmp configuaration as separate function so that code is more readable. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
2023-08-22lib: sbi_pmu: remove mhpm_count field in hart featureInochi Amaoto1-28/+18
After supporting noncontigous hpm event and counters in opensbi, the number of hpm counters can be calculated by the mhpm_mask. So this field is unnecessary and can be removed to save some space. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-08-18lib: sbi: Add support for smcntrpmfKaiwen Xue1-0/+11
This adds the support for ISA extension smcntrpmf. When some inhibit flags are set by a lower privilege mode for new CSRs added by smcntrpmf, OpenSBI sets the appropriate values correspondingly. Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu> Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2023-08-06lib: sbi_pmu: Enable noncontigous hpm event and countersMayuresh Chitale1-14/+42
Platforms may implement hpm events/counters non contiguously but the current implementation assumes them to be always contigous. Add a bitmap that captures the hpm events/counters as implemented in the hardware and use it to set the max limit of hardware counters visible to the OS. Counters not implemented in the hardware can't be used by the OS because those wont be described in the DT. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-07-13lib: sbi: Add functions to map/unmap shared memoryHimanshu Chauhan1-0/+42
When Smepmp is enabled, M-mode will need to map/unmap the shared memory before it can read/write to it. This patch adds functions to create dynamic short-lived mappings. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-07-13lib: sbi: Add support for SmepmpHimanshu Chauhan1-19/+115
- If Smepmp is enabled, the access flags of an entry are determined based on truth table defined in Smepmp. - First PMP entry (index 0) is reserved. - Existing boot PMP entries start from index 1. - Since enabling Smepmp revokes the access privileges of the M-mode software on S/U-mode region, first PMP entry is used to map/unmap the shared memory between M and S/U-mode. This allows a temporary access window for the M-mode software to read/write to S/U-mode memory region. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-07-13lib: sbi: Add smepmp in hart extensionsHimanshu Chauhan1-0/+3
- Add Smepmp as extension in sbi_hart_extensions enum - Return "smepmp" string for Smepmp extension from sbi_hart_extension_id2string Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-07-09lib: sbi: Fix Priv spec version for [m|s]counteren and mcountinhibit CSRsLey Foon Tan1-1/+1
Fix Priv spec version typo in commit d4b563c881d6 ("lib: sbi: Remove MCOUNTEREN and SCOUNTEREN hart features"). At least Priv spec v1.11 is required for [m|s]counteren and mcountinhibit CSRs. Fixes: d4b563c881d6 ("lib: sbi: Remove MCOUNTEREN and SCOUNTEREN hart features") Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-07-09lib: sbi: Rename hart_pmu_get_allowed_bits() functionAnup Patel1-2/+2
The hart_pmu_get_allowed_bits() function detects implemented bits of mhpm counters so let us rename this function accordingly. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com>
2023-07-09lib: sbi: Alphabetically sort HART ISA extensionsAnup Patel1-8/+8
Let us follow alphabetical order for HART ISA extension so that it is simpler to maintain. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com>
2023-07-09lib: sbi: Add Zihpm as a HART ISA extensionAnup Patel1-0/+8
Recently ratified Zihpm ISA extension covers all [m]hpm* CSRs so we add Zihpm as a HART ISA extension in OpenSBI. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com>
2023-07-09lib: sbi: Add Zicntr as a HART ISA extensionAnup Patel1-3/+3
Recently ratified Zicntr ISA extension covers cycle, time and instret CSRs so we replace the "time" ISA extension with "zicntr" ISA extension in OpenSBI. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com>
2023-04-06lib: sbi_hart: clear mip csr during hart initMayuresh Chitale1-0/+6
If mip.SEIP bit is not cleared then on HiFive Unmatched board it causes spurious external interrupts. This breaks the boot up of HiFive Unmatched board. Hence it is required to bring the mip CSR to a known state during hart init and avoid spurious interrupts. Fixes: d9e7368 ("firmware: Not to clear all the MIP") Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-02-27lib: sbi_hart: Enable hcontext and scontextNylon Chen1-0/+1
According to the description in "riscv-state-enable[0]", to access h/scontext in S-Mode, we need to enable the 57th bit. If it is not enabled, an "illegal instruction" error will occur. Link: https://github.com/riscv/riscv-state-enable/blob/a28bfae443f350d5b4c42874f428367d5b322ffe/content.adoc [0] Signed-off-by: Nylon Chen <nylon.chen@sifive.com> Reviewed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-01-09lib: sbi: Use finer permission sematics to decide on PMP bitsHimanshu Chauhan1-5/+11
Use the fine grained permission bits to decide if the region permissions are to be enforced on all modes. Also use the new permission bits for deciding on R/W/X bits in pmpcfg register. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anup Patel <anup@brainfault.org>
2022-12-09lib: sbi: Synchronize PMP settings with virtual memory systemHimanshu Chauhan1-0/+22
As per section 3.7.2 of RISC-V Privileged Specification, PMP settings must be synchronized with the virtual memory system after PMP settings have been written. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-10-13lib: sbi_platform: expose hart_features to extension_init callbackHeiko Stuebner1-1/+2
The platform-specific extension_init callback is supposed to set specific things for the platform opensbi is running on. So it's also the right place to override specific hart_features if needed - when it's know that autodetection has provided wrong results for example. Suggested-by: Atish Patra <atishp@atishpatra.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-10-13lib: sbi_hart: move hart_features struct to a public locationHeiko Stuebner1-23/+13
Platforms may need to override auto-detected hart features in their override functions. So move the hart_features struct to the sbi_hart.h header allowing us to pass it over to platform-handlers. Suggested-by: Atish Patra <atishp@atishpatra.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-10-13lib: sbi_pmu: move pmu irq information into pmu itselfHeiko Stuebner1-2/+2
Don't spread checking for pmu extensions through the code but instead introduce a sbi-pmu function that other code can call to get the correct information about the existence of the pmu interrupt. Add a sbi_pmu_device override function to allow overridung this bit as well if needed. Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-08-22lib: sbi: Use the official extension name for AIA M-mode CSRsAnup Patel1-4/+4
The arch review of AIA spec is completed and we now have official extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). Refer, section 1.6 of the latest AIA v0.3.1 stable specification at https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-interrupts-032.pdf) Based on above, we update generic library to use "Smaia" extension name for AIA M-mode CSRs. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-07-20lib: sbi_hart: Shorten the code to set MPV bitgagachang1-10/+3
MPV bit is set when the value of next_virt boolean variable equals true. Since the value of next_virt is either 0 or 1, we can set MPV bit without if-else logic. Signed-off-by: Che-Chia Chang <alvinga@andestech.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-07lib: sbi_platform: Add callback to populate HART extensionsAnup Patel1-4/+14
We add platform specific extensions_init() callback which allows platforms to populate HART extensions for each HART. For example, the generic platform can populate HART extensions from HART ISA string described in DeviceTree. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Add sbi_hart_update_extension() functionAnup Patel1-5/+38
We add sbi_hart_update_extension() function which allow platforms to enable/disable hart extensions. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Detect hart features only once for each hartAnup Patel1-3/+11
Currently, the hart_detect_features() is called everytime a hart is stopped and started again which is unnecessary work. We update hart_detect_features() to detect hart features only once for each hart. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Convert hart features into hart extensionsAnup Patel1-62/+54
Since past few years, we have been using "hart features" in OpenSBI to represent all optionalities and multi-letter extensions defined by the RISC-V specifications. The RISC-V profiles specification has taken a different approach and started assigning extension names for all optionalities which did not have any extension name previously. (Refer, https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) Inspired from the RISC-V profiles specification, we convert OpenSBI hart features into hart extensions. Going forward, we align the extension naming with RISC-V profiles specification. Currently, only "time CSR" and "AIA CSR" have not been assigned extension name but for everything else we have a name. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Fix AIA feature detectionAnup Patel1-4/+3
The AIA feature detection uses unnecessary goto which is not need and AIA case in sbi_hart_feature_id2string() does not break. This patch fixes both issues in AIA feature detection. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Remove MENVCFG hart featureAnup Patel1-20/+12
If a hart implements privileged spec v1.12 (or higher) then we can safely assume that menvcfg CSR is present and we don't need MENVCFG as a hart feature. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Remove MCOUNTINHIBT hart featureAnup Patel1-15/+8
If a hart implements privileged spec v1.11 (or higher) then we can safely assume that mcountinhibit CSR is present and we don't need MCOUNTINHIBT as a hart feature. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Remove MCOUNTEREN and SCOUNTEREN hart featuresAnup Patel1-24/+5
If a hart implements privileged spec v1.10 (or higher) then we can safely assume that [m|s]counteren CSR are present and we don't need MCOUNTEREN and SCOUNTEREN as hart features. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Detect and print privileged spec versionAnup Patel1-6/+46
It is possible to guess privileged spec versions based on the CSRs that where introduced in different privileged spec versions. In future, if we are not able guess privileged spec version then we can have platform provide it. We add privileged spec version as per-hart feature and try to guess it based on presence of mcounteren, mcountinhibit, and menvcfg CSRs. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
generated by cgit v1.1 at 2024-07-24 15:43:57 +0000