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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-09 19:51:55 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-01-13 17:16:04 +0100 |
| commit | a37506699109d2dbf86ec5c02734eee35d065d94 (patch) | |
| tree | d56607d11663faf567e169ff71c4eb052ab0fa19 /scripts/xml-preprocess.py | |
| parent | c629791859d5d1777d8471f260f418e76078e97e (diff) | |
| download | qemu-a37506699109d2dbf86ec5c02734eee35d065d94.zip qemu-a37506699109d2dbf86ec5c02734eee35d065d94.tar.gz qemu-a37506699109d2dbf86ec5c02734eee35d065d94.tar.bz2 | |
hw/net/xilinx_ethlite: Access TX_CTRL register for each port
Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_CTRL. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.
Previous s->regs[R_TX_CTRL0] and s->regs[R_TX_CTRL1] are now
unused. Not a concern, this array will soon disappear.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241112181044.92193-15-philmd@linaro.org>
Diffstat (limited to 'scripts/xml-preprocess.py')
0 files changed, 0 insertions, 0 deletions