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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-09 19:48:36 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-01-13 17:16:04 +0100 |
| commit | c629791859d5d1777d8471f260f418e76078e97e (patch) | |
| tree | cedc5dc0eabd7316d073eb5f85b81f30d50392e2 /scripts/xml-preprocess.py | |
| parent | 64fdbae7e1bc6408204a3cf3b8e6a2e7d8e36fe2 (diff) | |
| download | qemu-c629791859d5d1777d8471f260f418e76078e97e.zip qemu-c629791859d5d1777d8471f260f418e76078e97e.tar.gz qemu-c629791859d5d1777d8471f260f418e76078e97e.tar.bz2 | |
hw/net/xilinx_ethlite: Access TX_LEN register for each port
Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_LEN. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.
Previous s->regs[R_TX_LEN0] and s->regs[R_TX_LEN1] are now
unused. Not a concern, this array will soon disappear.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20241112181044.92193-14-philmd@linaro.org>
Diffstat (limited to 'scripts/xml-preprocess.py')
0 files changed, 0 insertions, 0 deletions