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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2025-03-07 11:59:14 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-03-09 14:36:53 +0100 |
| commit | 7ffee511fcf1487e016ae1d11c5e191557a8b804 (patch) | |
| tree | 8d38e148263c263112057393891d8d0234eda88b /docs/sphinx/compat.py | |
| parent | b008465d655ff3ff314fe1ef81031293b582ebaf (diff) | |
| download | qemu-7ffee511fcf1487e016ae1d11c5e191557a8b804.zip qemu-7ffee511fcf1487e016ae1d11c5e191557a8b804.tar.gz qemu-7ffee511fcf1487e016ae1d11c5e191557a8b804.tar.bz2 | |
hw/intc/aspeed: Reduce regs array size by adding a register sub-region
Currently, the size of the "regs" array is 0x2000, which is too large. So far,
it only uses "GICINT128 to `GICINT134", and the offsets from 0 to 0x1000 are
unused. To save code size and avoid mapping large unused gaps, update to only
map the useful set of registers:
INTC register [0x1000 – 0x1804]
Update "reg_size" to 0x808. Introduce a new class attribute "reg_offset" to set
the start offset of a "INTC" sub-region. Set the "reg_offset" to 0x1000 for INTC
registers.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-6-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'docs/sphinx/compat.py')
0 files changed, 0 insertions, 0 deletions