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2023-03-11[SPARC] Lower BR_CC to BPr on 64-bit target whenever possibleKoakuma11-55/+219
2023-03-11[SPARC] Implement hooks for conditional branch relaxationKoakuma10-45/+250
2023-03-11Revert "[InstCombine] use loop info when running the pass after loop vectoriz...Sanjay Patel8-35/+24
2023-03-11[InstCombine] use loop info when running the pass after loop vectorizationSanjay Patel8-24/+35
2023-03-11[X86] Add tests showing the failure to merge SHL/ADD through AND masks into LEASimon Pilgrim1-0/+45
2023-03-11[DAG] combineShiftAnd1ToBitTest - improve support for peeking through truncat...Simon Pilgrim2-27/+21
2023-03-11[DAG] Add test showing combineShiftAnd1ToBitTest failing to peek through a tr...Simon Pilgrim1-0/+16
2023-03-11[VPlan] Simplify code in createReplicateRegion (NFC).Florian Hahn1-11/+7
2023-03-10[test] Add some interesting cases to MC/RISCV/riscv64-64b-pcrel.sFangrui Song1-1/+23
2023-03-10[RISCV] Adjust how -1.0 is handled in RISCVLoadFPImm. NFCCraig Topper2-23/+26
2023-03-11[X86] Add unwind for base pointer test case.Luo, Yuanke2-2/+63
2023-03-10[RISCV] Remove one bit of mantissa in RISCVLoadFPImm related code.Craig Topper2-20/+20
2023-03-11[X86] Add regcall CC test case for base pointer register.Luo, Yuanke2-0/+163
2023-03-11[NVPTX] Sync generation of parameter names in a function signature with the f...Pavel Kopyl5-42/+60
2023-03-10[NFC] fix typo `funciton` -> `function`Yuanfang Chen11-11/+11
2023-03-10Add install targets for gtestTom Stellard3-4/+14
2023-03-10[Passes] Remove some legacy passesArthur Eubanks23-675/+5
2023-03-10[ASAN] Support memory checks on scalable vector typed masked load and storePhilip Reames2-25/+150
2023-03-10[llvm-tblgen] Support conditional definitions using !casts clausesPhilip Reames2-26/+37
2023-03-10Revert "[X86] Drop single use check for freeze(undef) in LowerAVXCONCAT_VECTORS"ManuelJBrito3-5/+17
2023-03-10[cmake] Quote args when generating /libpath option specifying runtime dir for...Matthew Voss1-1/+1
2023-03-10Revert "[MergeICmps] Adapt to non-eq comparisons, fix bug for cases need be s...Arthur Eubanks2-229/+18
2023-03-10[SLP]Initial support for reshuffling of non-starting buildvector/gather nodes.Alexey Bataev49-1244/+976
2023-03-10[Driver][FreeBSD] Simplify ARM handlingBrad Smith1-1/+1
2023-03-10[RISCV] Consistently place single quotes around extension names in error mess...Craig Topper1-5/+5
2023-03-10[SLP][NFC]Add a test with phi nodes in one tree node with differentAlexey Bataev1-0/+47
2023-03-10[Debuginfod] Prune cache after fetch.Daniel Thornburgh2-10/+56
2023-03-10[RISCV] Error if F and Zfinx extensions are specified together.Craig Topper1-0/+4
2023-03-10llvm-exegesis: Only run target specfic tests on native hostsTom Stellard2-0/+6
2023-03-10[SLP][NFC]Add a test with multilevel dependency between buildvectorAlexey Bataev1-0/+77
2023-03-10[ConstraintElimination] UB reproducer for D145677Vitaly Buka1-0/+13
2023-03-10MachO: support custom section names on global variablesTim Northover2-0/+42
2023-03-10Revert "[LICM] Support logical AND/OR when hoisting min/max"Vitaly Buka2-31/+17
2023-03-10[ConstraintElim] Update test to use variable start value.Florian Hahn1-3/+3
2023-03-10[RISCV] Support Zfa fli instructions with vector splats.Craig Topper4-21/+71
2023-03-10[VPlan] Add VPWidenSelectRecipe::getCond() (NFC).Florian Hahn2-3/+7
2023-03-10[RISCV] Enable Zfa fli.h instruction in MC layer with Zfhmin and Zvfh.Craig Topper3-1/+30
2023-03-10[SLP][NFC]Update/simplify test to avoid dead code elimination.Alexey Bataev1-77/+59
2023-03-10[RISCV] Print Zfa fli instruction FP values in a more adaptive way.Craig Topper5-108/+117
2023-03-10[TargetParser] Disallow Global ConstructorsArchibald Elliott1-0/+10
2023-03-10[DebugInfo][DWARF][NFC] follow LLVM style guideline about namespaces.Alexey Lapshin1-7/+1
2023-03-10[LICM] Delay fetching of preheader (NFC)Nikita Popov1-2/+2
2023-03-10[AArch64] NFC: Merge addTypeForStreamingSVE and addTypeForFixedLengthSVESander de Smalen2-144/+13
2023-03-10[GlobalOpt] Add test where the initializer evaluation fails.Florian Hahn1-0/+19
2023-03-10[gn build] Port 54178fc6161aLLVM GN Syncbot1-0/+1
2023-03-10[AMDGPU] Make use of defvar in defining SMEM Real instructionsJay Foad1-10/+9
2023-03-10[VPlan] Replace InvariantCond field from VPWidenSelectRecipe.Florian Hahn7-29/+19
2023-03-10[AArch64] Remove fixed FIXMEs from D120706. NFCDavid Green1-3/+3
2023-03-10[AMDGPU][MachineVerifier] Fix vdata reg count for MIMG d16Mirko Brkusanin2-4/+9
2023-03-10Revert "[SLP]Initial support for reshuffling of non-starting buildvector/gath...Hans Wennborg49-998/+1293
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