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AgeCommit message (Expand)AuthorFilesLines
2024-05-06[LoongArch] Optimize *W Instructions at MI level (#90463)hev1-0/+1
2024-05-04[TableGen] Use bitwise operations to access HwMode ID. (#88377)superZWT1233-31/+125
2024-05-03Revert "[gn] port 2d4acb086541 (LLVM_ENABLE_CURL)"Reid Kleckner1-7/+0
2024-05-03[docs,utils] Convert text files from CRLF to LFFangrui Song1-70/+70
2024-05-03[llvm-mca] Teach MCA constant registers do not create dependencies (#89387)Rin Dobrescu1-2/+3
2024-05-03[gn build] Port ed299b3efd66LLVM GN Syncbot1-0/+1
2024-05-03[GlobalISel] Optimize ULEB128 usage (#90565)Pierre van Houtryve1-2/+6
2024-05-02[gn build] Port 17f006207cb2LLVM GN Syncbot1-0/+2
2024-05-02[gn] port 2d4acb086541 (LLVM_ENABLE_CURL)Nico Weber1-0/+7
2024-05-02[gn build] Port c2d892668b7fLLVM GN Syncbot1-0/+1
2024-05-02[gn] port dcbf0fcd0d55 (SBLanguages.h python)Nico Weber2-11/+9
2024-05-02[gn] port f0fbccb15384Nico Weber1-1/+0
2024-05-01[RISCV] Use binary search to look up supported profiles. (#90767)Craig Topper1-1/+4
2024-05-01[z/OS] treat text files as text files so auto-conversion is done (#90128)Sean Perry2-2/+23
2024-05-01[AArch64][TargetParser] autogen ArchExtKind enum (#90314)Tomas Matheson1-0/+11
2024-05-01[gn build] Port df241b19c952LLVM GN Syncbot1-0/+1
2024-05-01Revert "[gn] port 088aa81a5454 (LLVM_HAS_LOGF128)"Nico Weber2-2/+0
2024-05-01[gn] port 088aa81a5454 (LLVM_HAS_LOGF128)Nico Weber2-0/+2
2024-05-01[gn] port 8cde1cfc60e3 (LLVM_APPEND_VC_REV for lit)Nico Weber1-0/+2
2024-04-30[gn build] Port a5cc95147ed5LLVM GN Syncbot1-0/+1
2024-04-30[gn build] Port 6ea0c0a28343LLVM GN Syncbot2-5/+2
2024-04-30[gn] port 975eca0e6a3 (-gen-lldb-sbapi-dwarf-enum)Nico Weber3-0/+13
2024-04-30Revert "[AArch64][TargetParser] autogen ArchExtKind enum (#90314)"Tomas Matheson1-11/+0
2024-04-30[AArch64][TargetParser] autogen ArchExtKind enum (#90314)Tomas Matheson1-0/+11
2024-04-29[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492)Kai Nacke1-21/+21
2024-04-29[TableGen][GISel] Handle frameindex/tframeindex (#90475)Kai Nacke1-0/+9
2024-04-28[RISCV] Generate profiles from RISCVProfiles.tdPengcheng Wang1-11/+29
2024-04-28[RISCV][TableGen] Get right experimental extension namePengcheng Wang1-1/+1
2024-04-28[gn build] Port 1a462296360fLLVM GN Syncbot1-0/+1
2024-04-27[CMake][Release] Enable CMAKE_POSITION_INDEPENDENT_CODE (#90139)Tom Stellard1-2/+1
2024-04-27[gn build] Port cb508a0032ebLLVM GN Syncbot1-0/+1
2024-04-26[RISCV] Move OrderedExtensionMap typedef to RISCVISAUtils.h. NFCCraig Topper1-3/+1
2024-04-26[RISCV] Flatten the ImpliedExts table in RISCVISAInfo.cpp (#89975)Craig Topper1-26/+4
2024-04-26Revert "[TableGen] Ignore inaccessible memory when checking pattern flags (#9...Jay Foad1-9/+1
2024-04-26[TableGen] Ignore inaccessible memory when checking pattern flags (#90061)Jay Foad1-1/+9
2024-04-26[NFC][llvm] refine generated code format (#90172)long.chen1-1/+1
2024-04-25LLVM_FALLTHROUGH => [[fallthrough]]. NFCFangrui Song1-2/+2
2024-04-25[TableGen] ShouldIgnore Pattern bit to disable DAG pattern imports during GIS...jofrn3-12/+20
2024-04-25[gn build] Port 8dc7db7a2463LLVM GN Syncbot1-0/+1
2024-04-25[gn build] Port d3f92e30bbd5LLVM GN Syncbot1-0/+1
2024-04-25[RISCV] Generate RISCVISAInfo table from RISCVFeatures.td. (#89955)Craig Topper1-4/+98
2024-04-25Fix NATVIS for llvm::PointerIntPairAaron Ballman1-3/+3
2024-04-24[gn] port 71c5964f5c0 (-gen-arm-target-def)Nico Weber2-2/+20
2024-04-24[gn] port b8e97f0768f2Nico Weber1-0/+1
2024-04-24[ARM] Add ARMTargetDefEmitter to llvm-tblgen sourceTomas Matheson1-0/+1
2024-04-24[ARM][AArch64] autogenerate header file for TargetParser from Target tablegen...Tomas Matheson2-0/+64
2024-04-24[gn build] Port cf328ff96dafLLVM GN Syncbot2-3/+5
2024-04-24[TableGen][GlobalISel] Specialize more MatchTable Opcodes (#89736)Pierre van Houtryve2-89/+163
2024-04-23[gn build] Port d56f08b2ba43LLVM GN Syncbot1-0/+1
2024-04-23[gn build] Port 733a87783cfaLLVM GN Syncbot4-2/+3
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