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2024-05-06Try to use non-volatile registers for `preserve_none` parameters (#88333)Brandt Bucher3-20/+61
2024-05-06[AArch64][GlobalISel] Common some shuffle mask functions.David Green7-244/+117
2024-05-06[X86] Add slow div64 tuning flag to Nehalem target (#91129)Simon Pilgrim2-1/+2
2024-05-06[SLP]Use last pointer instead of first for reversed strided stores.Alexey Bataev2-2/+6
2024-05-07[RISCV] Move RISCVDeadRegisterDefinitions to post vector regalloc (#90636)Luke Lau4-11/+22
2024-05-06[AArch64][GlobalISel] Addition GISel test coverage for shuffles. NFCDavid Green3-221/+549
2024-05-07[RISCV] Check dead flag on VL def op in RISCVCoalesceVSETVLI. NFC (#91168)Luke Lau1-3/+1
2024-05-06[SLP]Fix PR91025: correctly handle smin/smax of signed operands.Alexey Bataev2-13/+17
2024-05-06[SLP][NFC]Add a test with incorrect smin analysis for minimal bitwidth, NFC.Alexey Bataev1-0/+40
2024-05-06[AggressiveInstCombine] Fix strncmp inlining (#91204)Franklin Zhang2-1/+40
2024-05-06Revert "[AIX][CMake] Use top-level tools in llvm_ExternalProject_Add" (#91019)David Tenty1-3/+1
2024-05-06Revert "Reapply "Use an abbrev to reduce size of VALUE_GUID records in ThinLT...Jan Voung17-131/+99
2024-05-06[LAA] Add tests showing extra unnecessary runtime checks.Florian Hahn1-0/+143
2024-05-06[LAA] Update check line in test to fully match message.Florian Hahn1-1/+1
2024-05-06[X86] Fix -Wunused-function in X86ISelLowering.cpp (NFC)Jie Fu1-1/+1
2024-05-06[X86] Fix -Wsign-compare in X86ISelLowering.cpp (NFC)Jie Fu1-1/+1
2024-05-06[X86] Fold BLEND(PERMUTE(X),PERMUTE(Y)) -> PERMUTE(BLEND(X,Y)) (#90219)Simon Pilgrim18-14152/+12705
2024-05-06[SystemZ] Simplify f128 atomic load/store (#90977)Ulrich Weigand5-168/+174
2024-05-06[DAG] Fold bitreverse(shl/srl(bitreverse(x),y)) -> srl/shl(x,y) (#89897)Simon Pilgrim4-397/+57
2024-05-06[LoongArch] Rename some OptWInstrs functions. NFCWANG Rui2-28/+32
2024-05-06[LoongArch] Mark data type i32 are sign-extended. NFCWANG Rui1-9/+9
2024-05-06[LoongArch] Optimize *W Instructions at MI level (#90463)hev21-627/+1797
2024-05-06[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)Sameer Sahasrabuddhe17-232/+244
2024-05-06[InstCombine] Fix miscompilation caused by #90436 (#91133)Yingwei Zheng2-0/+75
2024-05-06Reapply "SystemZ: Fold copy of vector immediate to gr128" (#91099)Matt Arsenault3-0/+264
2024-05-06[AMDGPU] Fix typo in function nameJay Foad2-4/+4
2024-05-06SystemZ: Remove unnecessary REQUIRES asserts from testsMatt Arsenault3-16/+13
2024-05-06SystemZ: Remove redundant REQUIRES systemz from testMatt Arsenault1-1/+0
2024-05-06Revert "Remove redundant move in return statement" (#91169)Mehdi Amini2-5/+5
2024-05-06Reapply "AMDGPU: Implement llvm.set.rounding (#88587)" series (#91113)Matt Arsenault8-0/+1890
2024-05-06Remove redundant move in return statement (#90546)xiaoleis-nv2-5/+5
2024-05-06[RISCV] Use virtual registers for AVL instrs in coalesce-vsetvli.mir. NFCLuke Lau1-7/+11
2024-05-06[RISCV] Teach .option arch to support experimental extensions. (#89727)Yeting Kuo2-12/+24
2024-05-06[RISCV] Add RISCVCoalesceVSETVLI tests for removing dead AVLs. NFCLuke Lau1-0/+62
2024-05-05[ADT] Reimplement operator==(StringRef, StringRef) (NFC) (#91139)Kazu Hirata1-1/+5
2024-05-06[X86][FP16] Do not create VBROADCAST_LOAD for f16 without AVX2 (#91125)Phoebe Wang2-1/+40
2024-05-05[clang backend] In AArch64's DataLayout, specify a minimum function alignment...Doug Wyatt3-7/+18
2024-05-06[AArch64][SelectionDAG] Lower multiplication by a constant to shl+sub+shl+sub...Allen2-2/+103
2024-05-05X86FixupBWInsts: Remove redundant code. NFCFangrui Song1-3/+1
2024-05-05[Target] Use StringRef::operator== instead of StringRef::equals (NFC) (#91072...Kazu Hirata16-35/+36
2024-05-05[LAA] Directly pass DepChecker to getSource/getDestination (NFC).Florian Hahn4-13/+16
2024-05-05[X86] 2008-08-31-EH_RETURN32.ll - regenerate with update_llc_test_checks.pySimon Pilgrim1-19/+41
2024-05-05[X86] bypass-slow-division-64.ll - add udiv+urem test coverageSimon Pilgrim1-21/+198
2024-05-05Revert "[InlineCost] Correct the default branch cost for the switch statement...DianQK4-152/+49
2024-05-05[InlineCost] Correct the default branch cost for the switch statement (#85160)Quentin Dian4-49/+152
2024-05-05[X86] bypass-slow-division-64.ll - add optsize/minsize testsSimon Pilgrim1-4/+78
2024-05-05[X86] bypass-slow-division-64.ll - extend cpu test coverageSimon Pilgrim1-56/+102
2024-05-05[AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#...Weihang Fan2-1/+24
2024-05-05[X86][EVEX512] Add `HasEVEX512` when `NoVLX` used for 512-bit patterns (#91106)Phoebe Wang3-22/+43
2024-05-05[VectorCombine] shuffleToIdentity - guard against call instructions.David Green2-2/+91
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