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path: root/llvm/utils/TableGen/RegisterInfoEmitter.cpp
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2025-07-16[TableGen] Add a bitvector of members of CodeGenRegisterClass (#149122)Jay Foad1-1/+1
2025-06-15[TableGen] Use range-based for loops (NFC) (#144283)Kazu Hirata1-6/+6
2025-06-11[X86][BreakFalseDeps] Using reverse order for undef register selection (#137569)Phoebe Wang1-5/+5
2025-05-13[TableGen][CodeGen] Give every leaf register a unique regunit (#139526)Jay Foad1-0/+2
2025-05-12[NFC][TableGen] Use StringRef::str() instead of casting (#139332)Rahul Joshi1-5/+5
2025-04-16[llvm] Use llvm::append_range (NFC) (#135931)Kazu Hirata1-1/+1
2025-03-03[NFC]Make file-local cl::opt global variables static (#126486)chrisPyr1-1/+1
2025-02-17TableGen: Generate reverseComposeSubRegIndices (#127050)Matt Arsenault1-3/+51
2025-02-13TableGen: Add missing consts to CodeGenSubRegIndexMatt Arsenault1-4/+4
2025-01-28[TableGen] Use MCRegister::id() to avoid an implicit conversion from MCRegist...Craig Topper1-1/+1
2025-01-16[TableGen] Use std::pair instead of std::make_pair. NFC. (#123174)Jay Foad1-3/+2
2024-12-13[TableGen] Allow empty terminator in SequenceToOffsetTable (#119751)Sergei Barannikov1-10/+10
2024-12-12CodeGen: Eliminate dynamic relocations in the register superclass tables. (#1...Owen Anderson1-11/+8
2024-12-11Revert "CodeGen: Eliminate dynamic relocations in the register superclass tab...Owen Anderson1-8/+11
2024-12-11CodeGen: Eliminate dynamic relocations in the register superclass tables. (#1...Owen Anderson1-11/+8
2024-11-27Reland "[AArch64] Define high bits of FPR and GPR registers (take 2) (#114827)"Sander de Smalen1-3/+3
2024-11-22Revert "[AArch64] Define high bits of FPR and GPR registers (take 2) (#114827...Vitaly Buka1-3/+3
2024-11-14[AArch64] Define high bits of FPR and GPR registers (take 2) (#114827)Sander de Smalen1-3/+3
2024-10-18[LLVM][TableGen] Change all `Init` pointers to const (#112705)Rahul Joshi1-3/+3
2024-10-04[TableGen] Factor out timer code into a new `TGTimer` class (#111054)Rahul Joshi1-4/+6
2024-09-20[LLVM][TableGen] Change RegisterInfoEmitter to use const RecordKeeper (#109237)Rahul Joshi1-16/+13
2024-09-19[LLVM] Use {} instead of std::nullopt to initialize empty ArrayRef (#109133)Jay Foad1-2/+2
2024-09-18[NFC] Cleanup RegisterInfoEmitter code (#109199)Rahul Joshi1-51/+38
2024-09-18[Target] Use 'unsigned' as the underlying type for the tablegened physical re...Craig Topper1-1/+1
2024-09-15[LLVM][TableGen] Change CodeGenTarget to use const RecordKeeper (#108752)Rahul Joshi1-2/+1
2024-09-09[TableGen] Change SetTheory set/vec to use const Record * (#107692)Rahul Joshi1-15/+15
2024-08-06[X86][RA] Add two address hints for compressible NDD instructions. (#98603)Freddy Ye1-0/+16
2024-06-02[TableGen] Use llvm::unique (NFC) (#94163)Kazu Hirata1-5/+4
2024-05-03[llvm-mca] Teach MCA constant registers do not create dependencies (#89387)Rin Dobrescu1-2/+3
2024-03-27[Target][RISCV] Add HwMode support to subregister index size/offset. (#86368)Craig Topper1-5/+14
2024-03-25[RFC][TableGen] Restructure TableGen Source (#80847)Pierre van Houtryve1-6/+6
2024-03-22[Target] Move SubRegIdxRanges from MCSubtargetInfo to TargetInfo. (#86245)Craig Topper1-16/+13
2024-03-10Add llvm::min/max_element and use it in llvm/ and mlir/ directories. (#84678)Justin Lebar1-2/+2
2024-02-09[NFC] clang-format utils/TableGen (#80973)Pierre van Houtryve1-115/+111
2024-01-30[AMDGPU] Speed up SIRegisterInfo::getReservedRegs (#79844)Jay Foad1-1/+3
2024-01-25[llvm] Move CodeGenTypes library to its own directory (#79444)Nico Weber1-1/+1
2023-08-21Move VTList pointer out of RegClassInfosBenjamin Kramer1-2/+2
2023-08-14[CodeGen] Set regunitmasks for leaf regs to all instead of noneJay Foad1-6/+2
2023-08-03[TableGen][NFC] Refine obtaining qualified register class ids.Ivan Kosarev1-6/+4
2023-07-27[TableGen][RegisterInfoEmitter] Make entries of base register class tables hu...Ivan Kosarev1-21/+26
2023-07-05[RISCV][TableGen] Remove f32 from XLenFVT for RV32.Craig Topper1-2/+4
2023-06-04[CodeGen] Fix incorrect usage of MCPhysReg for diff list elementsSergei Barannikov1-42/+21
2023-05-23Revert "[CodeGen] Fix incorrect usage of MCPhysReg for diff list elements"Sergei Barannikov1-21/+42
2023-05-23[CodeGen] Fix incorrect usage of MCPhysReg for diff list elementsSergei Barannikov1-42/+21
2023-05-03Restore CodeGen/MachineValueType.h from `Support`NAKAMURA Takumi1-1/+1
2023-03-21llvm-tblgen: Rewrite emitters to use `TableGen::Emitter`NAKAMURA Takumi1-8/+2
2023-02-19llvm-tblgen: Add "TableGenBackends.h" to each emitter.NAKAMURA Takumi1-0/+1
2023-02-17llvm-tblgen: Apply IWYU partiallyNAKAMURA Takumi1-0/+2
2023-01-05Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ partserge-sans-paille1-4/+4
2022-12-20[TableGen] Emit table mapping physical registers to base classesCarl Ritson1-2/+54
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