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6 daysReapply "[llvm] Add CalleeTypeIds field to CallSiteInfo" (#150335) (#150990)Prabhu Rajasekaran1-3/+11
This reverts commit 05e08cdb3e576cc0887d1507ebd2f756460c7db7. Adding the missing -mtriple flags in MIR/X86 test files which caused these tests to fail which was the reason for reverting the patch.
11 daysRevert "[llvm] Add CalleeTypeIds field to CallSiteInfo" (#150335)Haowei1-11/+3
Reverts llvm/llvm-project#87574, which breaks LLVM :: CodeGen/MIR/X86/call-site-info-ambiguous-indirect-call-typeid.mir tests on linux-arm64 builders.
11 days[llvm] Add CalleeTypeIds field to CallSiteInfoPrabhu Rajasekaran1-3/+11
Introducing `EnableCallGraphSection` target option to add CalleeTypeIds field in CallSiteInfo. Read the callee type ids in and out by the MIR parser/printer. Reviewers: ilovepi Reviewed By: ilovepi Pull Request: https://github.com/llvm/llvm-project/pull/87574
2025-06-06[MIRParser] Report register class errors in a deterministic order (#142928)Jay Foad1-9/+19
2025-05-22[LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties ↵users/pcc/spr/main.elf-add-branch-to-branch-optimizationRahul Joshi1-10/+8
(#140002) Add per-property has<Prop>/set<Prop>/reset<Prop> functions to MachineFunctionProperties.
2025-03-06[win] NFC: Rename `EHCatchret` to `EHCont` to allow for EH Continuation ↵Daniel Paoliello1-1/+1
targets that aren't `catchret` instructions (#129953) This change splits out the renaming and comment updates from #129612 as a non-functional change.
2025-03-06[IR] Store Triple in Module (NFC) (#129868)Nikita Popov1-4/+4
The module currently stores the target triple as a string. This means that any code that wants to actually use the triple first has to instantiate a Triple, which is somewhat expensive. The change in #121652 caused a moderate compile-time regression due to this. While it would be easy enough to work around, I think that architecturally, it makes more sense to store the parsed Triple in the module, so that it can always be directly queried. For this change, I've opted not to add any magic conversions between std::string and Triple for backwards-compatibilty purses, and instead write out needed Triple()s or str()s explicitly. This is because I think a decent number of them should be changed to work on Triple as well, to avoid unnecessary conversions back and forth. The only interesting part in this patch is that the default triple is Triple("") instead of Triple() to preserve existing behavior. The former defaults to using the ELF object format instead of unknown object format. We should fix that as well.
2025-03-04[MIRParser] Use Register::id(). Pass Twine by reference. NFCCraig Topper1-2/+2
2025-03-02[CodeGen] Use Register::id() to avoid implicit cast. NFCCraig Topper1-1/+1
2025-01-13Reapply "[aarch64][win] Add support for import call optimization (equivalent ↵Daniel Paoliello1-12/+62
to MSVC /d2ImportCallOptimization) (#121516)" (#122777) This reverts commit 2f7ade4b5e399962e18f5f9a0ab0b7335deece51. Fix is available in #122762
2025-01-13Revert "[aarch64][win] Add support for import call optimization (equivalent ↵Kirill Stoimenov1-62/+12
to MSVC /d2ImportCallOptimization) (#121516)" Breaks sanitizer build: https://lab.llvm.org/buildbot/#/builders/52/builds/5179 This reverts commits: 5ee0a71df919a328c714e25f0935c21e586cc18b d997a722c194feec5f3a94dec5acdce59ac5e55b
2025-01-11[aarch64][win] Add support for import call optimization (equivalent to MSVC ↵Daniel Paoliello1-12/+62
/d2ImportCallOptimization) (#121516) This change implements import call optimization for AArch64 Windows (equivalent to the undocumented MSVC `/d2ImportCallOptimization` flag). Import call optimization adds additional data to the binary which can be used by the Windows kernel loader to rewrite indirect calls to imported functions as direct calls. It uses the same [Dynamic Value Relocation Table mechanism that was leveraged on x64 to implement `/d2GuardRetpoline`](https://techcommunity.microsoft.com/blog/windowsosplatform/mitigating-spectre-variant-2-with-retpoline-on-windows/295618). The change to the obj file is to add a new `.impcall` section with the following layout: ```cpp // Per section that contains calls to imported functions: // uint32_t SectionSize: Size in bytes for information in this section. // uint32_t Section Number // Per call to imported function in section: // uint32_t Kind: the kind of imported function. // uint32_t BranchOffset: the offset of the branch instruction in its // parent section. // uint32_t TargetSymbolId: the symbol id of the called function. ``` NOTE: If the import call optimization feature is enabled, then the `.impcall` section must be emitted, even if there are no calls to imported functions. The implementation is split across a few parts of LLVM: * During AArch64 instruction selection, the `GlobalValue` for each call to a global is recorded into the Extra Information for that node. * During lowering to machine instructions, the called global value for each call is noted in its containing `MachineFunction`. * During AArch64 asm printing, if the import call optimization feature is enabled: - A (new) `.impcall` directive is emitted for each call to an imported function. - The `.impcall` section is emitted with its magic header (but is not filled in). * During COFF object writing, the `.impcall` section is filled in based on each `.impcall` directive that were encountered. The `.impcall` section can only be filled in when we are writing the COFF object as it requires the actual section numbers, which are only assigned at that point (i.e., they don't exist during asm printing). I had tried to avoid using the Extra Information during instruction selection and instead implement this either purely during asm printing or in a `MachineFunctionPass` (as suggested in [on the forums](https://discourse.llvm.org/t/design-gathering-locations-of-instructions-to-emit-into-a-section/83729/3)) but this was not possible due to how loading and calling an imported function works on AArch64. Specifically, they are emitted as `ADRP` + `LDR` (to load the symbol) then a `BR` (to do the call), so at the point when we have machine instructions, we would have to work backwards through the instructions to discover what is being called. An initial prototype did work by inspecting instructions; however, it didn't correctly handle the case where the same function was called twice in a row, which caused LLVM to elide the `ADRP` + `LDR` and reuse the previously loaded address. Worse than that, sometimes for the double-call case LLVM decided to spill the loaded address to the stack and then reload it before making the second call. So, instead of trying to implement logic to discover where the value in a register came from, I instead recorded the symbol being called at the last place where it was easy to do: instruction selection.
2024-11-14Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)Matin Raayai1-3/+3
Following discussions in #110443, and the following earlier discussions in https://lists.llvm.org/pipermail/llvm-dev/2017-October/117907.html, https://reviews.llvm.org/D38482, https://reviews.llvm.org/D38489, this PR attempts to overhaul the `TargetMachine` and `LLVMTargetMachine` interface classes. More specifically: 1. Makes `TargetMachine` the only class implemented under `TargetMachine.h` in the `Target` library. 2. `TargetMachine` contains target-specific interface functions that relate to IR/CodeGen/MC constructs, whereas before (at least on paper) it was supposed to have only IR/MC constructs. Any Target that doesn't want to use the independent code generator simply does not implement them, and returns either `false` or `nullptr`. 3. Renames `LLVMTargetMachine` to `CodeGenCommonTMImpl`. This renaming aims to make the purpose of `LLVMTargetMachine` clearer. Its interface was moved under the CodeGen library, to further emphasis its usage in Targets that use CodeGen directly. 4. Makes `TargetMachine` the only interface used across LLVM and its projects. With these changes, `CodeGenCommonTMImpl` is simply a set of shared function implementations of `TargetMachine`, and CodeGen users don't need to static cast to `LLVMTargetMachine` every time they need a CodeGen-specific feature of the `TargetMachine`. 5. More importantly, does not change any requirements regarding library linking. cc @arsenm @aeubanks
2024-10-16[MIR] Fix vreg flag vector memory leak (#112479)Akshat Oke1-1/+1
A fix-it patch for dbfca24 #110228. No need for a container. This allows 8 flags for a register. The virtual register flags vector had a memory leak because the vector's memory is not freed. The `BumpPtrAllocator` handles the deallocation and missed calling the `std::vector<uint8_t> Flags` destructor.
2024-10-14[MIR] Add missing noteNewVirtualRegister callbacks (#111634)Akshat Oke1-0/+1
The delegates' callback isn't invoked on parsing new virtual registers. There are two places in the serialization where new virtual registers can be discovered: in register infos and in instructions.
2024-10-14[MIR] Serialize virtual register flags (#110228)Akshat Oke1-0/+9
[MIR] Serialize virtual register flags This introduces target-specific vreg flag serialization. Flags are represented as `uint8_t` and the `TargetRegisterInfo` override provides methods `getVRegFlagValue` to deserialize and `getVRegFlagsOfReg` to serialize.
2024-10-04[LLVM] Add HasFakeUses to MachineFunction (#110097)Stephen Tozer1-0/+13
Following the addition of the llvm.fake.use intrinsic and corresponding MIR instruction, two further changes are planned: to add an -fextend-lifetimes flag to Clang that emits these intrinsics, and to have -Og enable this flag by default. Currently, some logic for handling fake uses is gated by the optdebug attribute, which is intended to be switched on by -fextend-lifetimes (and by extension -Og later on). However, the decision was made that a general optdebug attribute should be incompatible with other opt_ attributes (e.g. optsize, optnone), since they all express different intents for how to optimize the program. We would still like to allow -fextend-lifetimes with optsize however (i.e. -Os -fextend-lifetimes should be legal), since it may be a useful configuration and there is no technical reason to not allow it. This patch resolves this by tracking MachineFunctions that have fake uses, allowing us to run passes that interact with them and skip passes that clash with them.
2024-09-25Reapply "Deprecate the `-fbasic-block-sections=labels` option." (#110039)Rahman Lavaee1-3/+1
This reapplies commit 1911a50fae8a441b445eb835b98950710d28fc88 with a minor fix in lld/ELF/LTO.cpp which sets Options.BBAddrMap when `--lto-basic-block-sections=labels` is passed.
2024-09-25Revert "Deprecate the `-fbasic-block-sections=labels` option. (#107494)"Kazu Hirata1-1/+3
This reverts commit 1911a50fae8a441b445eb835b98950710d28fc88. Several bots are failing: https://lab.llvm.org/buildbot/#/builders/190/builds/6519 https://lab.llvm.org/buildbot/#/builders/3/builds/5248 https://lab.llvm.org/buildbot/#/builders/18/builds/4463
2024-09-25Deprecate the `-fbasic-block-sections=labels` option. (#107494)Rahman Lavaee1-3/+1
This feature is supported via the newer option `-fbasic-block-address-map`. Using the old option still works by delegating to the newer option, while a warning is printed to show deprecation.
2024-09-25[MIR] Fix return value when computed properties conflict with given prop ↵Dominik Montada1-2/+2
(#109923) This fixes a test failure when expensive checks are enabled. Use the correct return value when computing machine function properties resulted in an error (e.g. when conflicting with explicitly set values). Without this, the machine verifier would crash even in the presence of parsing errors which should have gently terminated execution.
2024-09-24llvm-reduce: Don't print verifier failed machine functions (#109673)Matt Arsenault1-1/+1
This produces far too much terminal output, particularly for the instruction reduction. Since it doesn't consider the liveness of of the instructions it's deleting, it produces quite a lot of verifier errors.
2024-09-24[MIR] Allow overriding isSSA, noPhis, noVRegs in MIR input (#108546)Dominik Montada1-11/+41
Allow setting the computed properties IsSSA, NoPHIs, NoVRegs for MIR functions in MIR input. The default value is still the computed value. If the property is set to false, the computed result is ignored. Conflicting values (e.g. setting IsSSA where the input MIR is clearly not SSA) lead to an error. Closes #37787
2024-09-19[LLVM] Use {} instead of std::nullopt to initialize empty ArrayRef (#109133)Jay Foad1-1/+1
It is almost always simpler to use {} instead of std::nullopt to initialize an empty ArrayRef. This patch changes all occurrences I could find in LLVM itself. In future the ArrayRef(std::nullopt_t) constructor could be deprecated or removed.
2024-05-01[MIR] Serialize MachineFrameInfo::isCalleeSavedInfoValid() (#90561)David Tellenbach1-0/+1
In case of functions without a stack frame no "stack" field is serialized into MIR which leads to isCalleeSavedInfoValid being false when reading a MIR file back in. To fix this we should serialize MachineFrameInfo::isCalleeSavedInfoValid() into MIR.
2024-04-30[NewPM][CodeGen] Add `MachineFunctionAnalysis` (#88610)paperchalice1-12/+36
In new pass system, `MachineFunction` could be an analysis result again, machine module pass can now fetch them from analysis manager. `MachineModuleInfo` no longer owns them. Remove `FreeMachineFunctionPass`, replaced by `InvalidateAnalysisPass<MachineFunctionAnalysis>`. Now `FreeMachineFunction` is replaced by `InvalidateAnalysisPass<MachineFunctionAnalysis>`, the workaround in `MachineFunctionPassManager` is no longer needed, there is no difference between `unittests/MIR/PassBuilderCallbacksTest.cpp` and `unittests/IR/PassBuilderCallbacksTest.cpp`.
2024-04-02[CallSiteInfo][NFC] CallSiteInfo -> CallSiteInfo.ArgRegPairs (#86842)Prabhuk1-2/+2
CallSiteInfo is originally used only for argument - register pairs. Make it struct, in which we can store additional data for call sites. Also, the variables/methods used for CallSiteInfo are named for its original use case, e.g., CallFwdRegsInfo. Refactor these for the upcoming use, e.g. addCallArgsForwardingRegs() -> addCallSiteInfo(). An upcoming patch will add type ids for indirect calls to propogate them from middle-end to the back-end. The type ids will be then used to emit the call graph section. Original RFC: https://lists.llvm.org/pipermail/llvm-dev/2021-June/151044.html Updated RFC: https://lists.llvm.org/pipermail/llvm-dev/2021-July/151739.html Differential Revision: https://reviews.llvm.org/D107109?id=362888 Co-authored-by: Necip Fazil Yildiran <necip@google.com>
2024-03-11[CodeGen] Do not pass MF into MachineRegisterInfo methods. NFC. (#84770)Jay Foad1-1/+1
MachineRegisterInfo already knows the MF so there is no need to pass it in as an argument.
2024-02-03[MIRParser] Simplify a string comparison (NFC)Kazu Hirata1-1/+1
2023-10-13[llvm] Stop including llvm/ADT/StringMap.h (NFC)Kazu Hirata1-1/+0
These source files do not use StringMap.
2023-05-28use ref to avoid copy in range for-loopWang, Xin101-1/+1
Use big obj copy in range for-loop will call copy constructor every time, which can be avoided by use ref instead. Reviewed By: skan Differential Revision: https://reviews.llvm.org/D150024
2023-05-11[YamlMF] Serialize EntryValueObjectsFelipe de Azevedo Piovezan1-0/+18
This commit implements the serialization and deserialization of the Machine Function's EntryValueObjects. Depends on D149879, D149778 Differential Revision: https://reviews.llvm.org/D149880
2023-05-04[MIRParser][nfc] Factor out code parsing debug MD nodesFelipe de Azevedo Piovezan1-16/+37
This commit splits a function that both parses MD nodes from YAML into DI{Expr,Loc,Variable} objects AND adds an entry to the MF variable table, so that each of those jobs is done separately. It will enable subsequent patches to reuse the MD node parsing code. Differential Revision: https://reviews.llvm.org/D149870
2023-04-10[MachineOutliner] Add IsOutlined to MachineFunctionwangpc1-0/+1
We add a field `IsOutlined` to indicate whether a MachineFunction is outlined and set it true for outlined functions in MachineOutliner. Reviewed By: paquette Differential Revision: https://reviews.llvm.org/D146191
2023-01-20[DebugInfo] Store instr-ref mode of MachineFunction in memberJeremy Morse1-0/+3
Add a flag state (and a MIR key) to MachineFunctions indicating whether they contain instruction referencing debug-info or not. Whether DBG_VALUEs or DBG_INSTR_REFs are used needs to be determined by LiveDebugValues at least, and using the current optimisation level as a proxy is proving unreliable. Test updates are purely adding the flag to tests, in a couple of cases it involves separating out VarLocBasedLDV/InstrRefBasedLDV tests into separate files, as they can no longer share the same input. Differential Revision: https://reviews.llvm.org/D141387
2023-01-12[IR] Support importing modules with invalid data layouts.Jannik Silvanus1-2/+4
Use the existing mechanism to change the data layout using callbacks. Before this patch, we had a callback type DataLayoutCallbackTy that receives a single StringRef specifying the target triple, and optionally returns the data layout string to be used. Module loaders (both IR and BC) then apply the callback to potentially override the module's data layout, after first having imported and parsed the data layout from the file. We can't do the same to fix invalid data layouts, because the import will already fail, before the callback has a chance to fix it. Instead, module loaders now tentatively parse the data layout into a string, wait until the target triple has been parsed, apply the override callback to the imported string and only then parse the tentative string as a data layout. Moreover, add the old data layout string S as second argument to the callback, in addition to the already existing target triple argument. S is either the default data layout string in case none is specified, or the data layout string specified in the module, possibly after auto-upgrades (for the BitcodeReader). This allows callbacks to inspect the old data layout string, and fix it instead of setting a fixed data layout. Also allow to pass data layout override callbacks to lazy bitcode module loader functions. Differential Revision: https://reviews.llvm.org/D140985
2022-12-22MIR: Don't assert if a virtual register uses a non-allocatable classMatt Arsenault1-2/+11
2022-12-02[CodeGen] Use std::nullopt instead of None (NFC)Kazu Hirata1-1/+1
This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-07-17[CodeGen] Qualify auto variables in for loops (NFC)Kazu Hirata1-2/+2
2022-06-20[llvm] Don't use Optional::getValue (NFC)Kazu Hirata1-2/+2
2022-06-18[llvm] Use value_or instead of getValueOr (NFC)Kazu Hirata1-1/+1
2022-04-22MIR: Serialize FunctionContextIdx in MachineFrameInfoMatt Arsenault1-0/+9
2022-04-15MIR: Serialize a few bool function fieldsMatt Arsenault1-0/+6
2022-03-23Cleanup include: codegen second roundserge-sans-paille1-3/+0
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D122180
2022-03-12Cleanup includes: DebugInfo & CodeGenserge-sans-paille1-4/+6
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121332
2022-03-01[nfc][codegen] Move RegisterBank[Info].h under CodeGenMircea Trofin1-2/+2
This wraps up from D119053. The 2 headers are moved as described, fixed file headers and include guards, updated all files where the old paths were detected (simple grep through the repo), and `clang-format`-ed it all. Differential Revision: https://reviews.llvm.org/D119876
2022-02-06[CodeGen] Use = default (NFC)Kazu Hirata1-1/+1
Identified with modernize-use-equals-default
2022-01-07[llvm] Remove redundant member initialization (NFC)Kazu Hirata1-2/+1
Identified with readability-redundant-member-init.
2022-01-03Revert "[llvm] Remove redundant member initialization (NFC)"Kazu Hirata1-1/+2
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3. This patch causes gcc to issue a lot of warnings like: warning: base class ‘class llvm::MCParsedAsmOperand’ should be explicitly initialized in the copy constructor [-Wextra]
2022-01-01[llvm] Remove redundant member initialization (NFC)Kazu Hirata1-2/+1
Identified with readability-redundant-member-init.