diff options
Diffstat (limited to 'llvm')
56 files changed, 418 insertions, 102 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h index 4762494..25a66cb 100644 --- a/llvm/include/llvm/CodeGen/MachineScheduler.h +++ b/llvm/include/llvm/CodeGen/MachineScheduler.h @@ -98,6 +98,12 @@ #include <vector> namespace llvm { +namespace impl_detail { +// FIXME: Remove these declarations once RegisterClassInfo is queryable as an +// analysis. +class MachineSchedulerImpl; +class PostMachineSchedulerImpl; +} // namespace impl_detail namespace MISched { enum Direction { @@ -1385,6 +1391,34 @@ std::unique_ptr<ScheduleDAGMutation> createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI); +class MachineSchedulerPass : public PassInfoMixin<MachineSchedulerPass> { + // FIXME: Remove this member once RegisterClassInfo is queryable as an + // analysis. + std::unique_ptr<impl_detail::MachineSchedulerImpl> Impl; + const TargetMachine *TM; + +public: + MachineSchedulerPass(const TargetMachine *TM); + MachineSchedulerPass(MachineSchedulerPass &&Other); + ~MachineSchedulerPass(); + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + +class PostMachineSchedulerPass + : public PassInfoMixin<PostMachineSchedulerPass> { + // FIXME: Remove this member once RegisterClassInfo is queryable as an + // analysis. + std::unique_ptr<impl_detail::PostMachineSchedulerImpl> Impl; + const TargetMachine *TM; + +public: + PostMachineSchedulerPass(const TargetMachine *TM); + PostMachineSchedulerPass(PostMachineSchedulerPass &&Other); + ~PostMachineSchedulerPass(); + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; } // end namespace llvm #endif // LLVM_CODEGEN_MACHINESCHEDULER_H diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index 6d74d7f..b8df4d1 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -209,7 +209,7 @@ void initializeMachinePipelinerPass(PassRegistry &); void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &); void initializeMachineRegionInfoPassPass(PassRegistry &); void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &); -void initializeMachineSchedulerPass(PassRegistry &); +void initializeMachineSchedulerLegacyPass(PassRegistry &); void initializeMachineSinkingPass(PassRegistry &); void initializeMachineTraceMetricsWrapperPassPass(PassRegistry &); void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &); @@ -238,7 +238,7 @@ void initializePostDomPrinterWrapperPassPass(PassRegistry &); void initializePostDomViewerWrapperPassPass(PassRegistry &); void initializePostDominatorTreeWrapperPassPass(PassRegistry &); void initializePostInlineEntryExitInstrumenterPass(PassRegistry &); -void initializePostMachineSchedulerPass(PassRegistry &); +void initializePostMachineSchedulerLegacyPass(PassRegistry &); void initializePostRAHazardRecognizerPass(PassRegistry &); void initializePostRAMachineSinkingPass(PassRegistry &); void initializePostRASchedulerLegacyPass(PassRegistry &); diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 7f91dd7e..1458318 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -50,6 +50,7 @@ #include "llvm/CodeGen/MachineLICM.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachinePassManager.h" +#include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/MachineVerifier.h" #include "llvm/CodeGen/OptimizePHIs.h" #include "llvm/CodeGen/PHIElimination.h" @@ -960,7 +961,7 @@ Error CodeGenPassBuilder<Derived, TargetMachineT>::addMachinePasses( if (getOptLevel() != CodeGenOptLevel::None && !TM.targetSchedulesPostRAScheduling()) { if (Opt.MISchedPostRA) - addPass(PostMachineSchedulerPass()); + addPass(PostMachineSchedulerPass(&TM)); else addPass(PostRASchedulerPass(&TM)); } @@ -1144,7 +1145,7 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addOptimizedRegAlloc( addPass(RenameIndependentSubregsPass()); // PreRA instruction scheduling. - addPass(MachineSchedulerPass()); + addPass(MachineSchedulerPass(&TM)); if (derived().addRegAssignmentOptimized(addPass)) { // Allow targets to expand pseudo instructions depending on the choice of diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index 9f9922d..075ebcb 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -142,12 +142,14 @@ MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass()) MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass()) MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass()) MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass()) +MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass(TM)) MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass()) MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass()) MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass()) MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass()) MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass()) MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass(TM)) +MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass(TM)) MACHINE_FUNCTION_PASS("print", PrintMIRPass()) MACHINE_FUNCTION_PASS("print<livedebugvars>", LiveDebugVariablesPrinterPass(errs())) MACHINE_FUNCTION_PASS("print<live-intervals>", LiveIntervalsPrinterPass(errs())) @@ -243,13 +245,11 @@ DUMMY_MACHINE_FUNCTION_PASS("static-data-splitter", StaticDataSplitter) DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass) DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass) DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata) -DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass) DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass) DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass) DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass) DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass) DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass) -DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass) DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass) DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass) DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass) diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp index d69a24f..35df2a47 100644 --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -94,7 +94,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeModuloScheduleTestPass(Registry); initializeMachinePostDominatorTreeWrapperPassPass(Registry); initializeMachineRegionInfoPassPass(Registry); - initializeMachineSchedulerPass(Registry); + initializeMachineSchedulerLegacyPass(Registry); initializeMachineSinkingPass(Registry); initializeMachineUniformityAnalysisPassPass(Registry); initializeMachineUniformityInfoPrinterPassPass(Registry); @@ -105,7 +105,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializePHIEliminationPass(Registry); initializePatchableFunctionPass(Registry); initializePeepholeOptimizerLegacyPass(Registry); - initializePostMachineSchedulerPass(Registry); + initializePostMachineSchedulerLegacyPass(Registry); initializePostRAHazardRecognizerPass(Registry); initializePostRAMachineSinkingPass(Registry); initializePostRASchedulerLegacyPass(Registry); diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 3f72e84..1be7a33 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -214,69 +214,119 @@ MachineSchedContext::~MachineSchedContext() { delete RegClassInfo; } -namespace { - -/// Base class for a machine scheduler class that can run at any point. -class MachineSchedulerBase : public MachineSchedContext, - public MachineFunctionPass { -public: - MachineSchedulerBase(char &ID) : MachineFunctionPass(ID) {} +namespace llvm { +namespace impl_detail { +/// Base class for the machine scheduler classes. +class MachineSchedulerBase : public MachineSchedContext { protected: void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags); }; -/// MachineScheduler runs after coalescing and before register allocation. -class MachineScheduler : public MachineSchedulerBase { -public: - MachineScheduler(); +/// Impl class for MachineScheduler. +class MachineSchedulerImpl : public MachineSchedulerBase { + // These are only for using MF.verify() + // remove when verify supports passing in all analyses + MachineFunctionPass *P = nullptr; + MachineFunctionAnalysisManager *MFAM = nullptr; - void getAnalysisUsage(AnalysisUsage &AU) const override; +public: + struct RequiredAnalyses { + MachineLoopInfo &MLI; + MachineDominatorTree &MDT; + AAResults &AA; + LiveIntervals &LIS; + }; - bool runOnMachineFunction(MachineFunction&) override; + MachineSchedulerImpl() {} + // Migration only + void setLegacyPass(MachineFunctionPass *P) { this->P = P; } + void setMFAM(MachineFunctionAnalysisManager *MFAM) { this->MFAM = MFAM; } - static char ID; // Class identification, replacement for typeinfo + bool run(MachineFunction &MF, const TargetMachine &TM, + const RequiredAnalyses &Analyses); protected: ScheduleDAGInstrs *createMachineScheduler(); }; -/// PostMachineScheduler runs after shortly before code emission. -class PostMachineScheduler : public MachineSchedulerBase { +/// Impl class for PostMachineScheduler. +class PostMachineSchedulerImpl : public MachineSchedulerBase { + // These are only for using MF.verify() + // remove when verify supports passing in all analyses + MachineFunctionPass *P = nullptr; + MachineFunctionAnalysisManager *MFAM = nullptr; + public: - PostMachineScheduler(); + struct RequiredAnalyses { + MachineLoopInfo &MLI; + AAResults &AA; + }; + PostMachineSchedulerImpl() {} + // Migration only + void setLegacyPass(MachineFunctionPass *P) { this->P = P; } + void setMFAM(MachineFunctionAnalysisManager *MFAM) { this->MFAM = MFAM; } - void getAnalysisUsage(AnalysisUsage &AU) const override; + bool run(MachineFunction &Func, const TargetMachine &TM, + const RequiredAnalyses &Analyses); + +protected: + ScheduleDAGInstrs *createPostMachineScheduler(); +}; +} // namespace impl_detail +} // namespace llvm + +using impl_detail::MachineSchedulerBase; +using impl_detail::MachineSchedulerImpl; +using impl_detail::PostMachineSchedulerImpl; + +namespace { +/// MachineScheduler runs after coalescing and before register allocation. +class MachineSchedulerLegacy : public MachineFunctionPass { + MachineSchedulerImpl Impl; + +public: + MachineSchedulerLegacy(); + void getAnalysisUsage(AnalysisUsage &AU) const override; bool runOnMachineFunction(MachineFunction&) override; static char ID; // Class identification, replacement for typeinfo +}; -protected: - ScheduleDAGInstrs *createPostMachineScheduler(); +/// PostMachineScheduler runs after shortly before code emission. +class PostMachineSchedulerLegacy : public MachineFunctionPass { + PostMachineSchedulerImpl Impl; + +public: + PostMachineSchedulerLegacy(); + void getAnalysisUsage(AnalysisUsage &AU) const override; + bool runOnMachineFunction(MachineFunction &) override; + + static char ID; // Class identification, replacement for typeinfo }; } // end anonymous namespace -char MachineScheduler::ID = 0; +char MachineSchedulerLegacy::ID = 0; -char &llvm::MachineSchedulerID = MachineScheduler::ID; +char &llvm::MachineSchedulerID = MachineSchedulerLegacy::ID; -INITIALIZE_PASS_BEGIN(MachineScheduler, DEBUG_TYPE, +INITIALIZE_PASS_BEGIN(MachineSchedulerLegacy, DEBUG_TYPE, "Machine Instruction Scheduler", false, false) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) -INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE, +INITIALIZE_PASS_END(MachineSchedulerLegacy, DEBUG_TYPE, "Machine Instruction Scheduler", false, false) -MachineScheduler::MachineScheduler() : MachineSchedulerBase(ID) { - initializeMachineSchedulerPass(*PassRegistry::getPassRegistry()); +MachineSchedulerLegacy::MachineSchedulerLegacy() : MachineFunctionPass(ID) { + initializeMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry()); } -void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const { +void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); AU.addRequired<MachineDominatorTreeWrapperPass>(); AU.addRequired<MachineLoopInfoWrapperPass>(); @@ -289,23 +339,24 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const { MachineFunctionPass::getAnalysisUsage(AU); } -char PostMachineScheduler::ID = 0; +char PostMachineSchedulerLegacy::ID = 0; -char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID; +char &llvm::PostMachineSchedulerID = PostMachineSchedulerLegacy::ID; -INITIALIZE_PASS_BEGIN(PostMachineScheduler, "postmisched", +INITIALIZE_PASS_BEGIN(PostMachineSchedulerLegacy, "postmisched", "PostRA Machine Instruction Scheduler", false, false) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) -INITIALIZE_PASS_END(PostMachineScheduler, "postmisched", +INITIALIZE_PASS_END(PostMachineSchedulerLegacy, "postmisched", "PostRA Machine Instruction Scheduler", false, false) -PostMachineScheduler::PostMachineScheduler() : MachineSchedulerBase(ID) { - initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry()); +PostMachineSchedulerLegacy::PostMachineSchedulerLegacy() + : MachineFunctionPass(ID) { + initializePostMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry()); } -void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const { +void PostMachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); AU.addRequired<MachineDominatorTreeWrapperPass>(); AU.addRequired<MachineLoopInfoWrapperPass>(); @@ -385,17 +436,14 @@ nextIfDebug(MachineBasicBlock::iterator I, } /// Instantiate a ScheduleDAGInstrs that will be owned by the caller. -ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() { +ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() { // Select the scheduler, or set the default. MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt; if (Ctor != useDefaultMachineSched) return Ctor(this); - const TargetMachine &TM = - getAnalysis<TargetPassConfig>().getTM<TargetMachine>(); - // Get the default scheduler set by the target for this function. - ScheduleDAGInstrs *Scheduler = TM.createMachineScheduler(this); + ScheduleDAGInstrs *Scheduler = TM->createMachineScheduler(this); if (Scheduler) return Scheduler; @@ -403,14 +451,47 @@ ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() { return createGenericSchedLive(this); } +bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM, + const RequiredAnalyses &Analyses) { + MF = &Func; + MLI = &Analyses.MLI; + MDT = &Analyses.MDT; + this->TM = &TM; + AA = &Analyses.AA; + LIS = &Analyses.LIS; + + if (VerifyScheduling) { + LLVM_DEBUG(LIS->dump()); + const char *MSchedBanner = "Before machine scheduling."; + if (P) + MF->verify(P, MSchedBanner, &errs()); + else + MF->verify(*MFAM, MSchedBanner, &errs()); + } + RegClassInfo->runOnMachineFunction(*MF); + + // Instantiate the selected scheduler for this target, function, and + // optimization level. + std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler()); + scheduleRegions(*Scheduler, false); + + LLVM_DEBUG(LIS->dump()); + if (VerifyScheduling) { + const char *MSchedBanner = "After machine scheduling."; + if (P) + MF->verify(P, MSchedBanner, &errs()); + else + MF->verify(*MFAM, MSchedBanner, &errs()); + } + return true; +} + /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by /// the caller. We don't have a command line option to override the postRA /// scheduler. The Target must configure it. -ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() { - const TargetMachine &TM = - getAnalysis<TargetPassConfig>().getTM<TargetMachine>(); +ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() { // Get the postRA scheduler set by the target for this function. - ScheduleDAGInstrs *Scheduler = TM.createPostMachineScheduler(this); + ScheduleDAGInstrs *Scheduler = TM->createPostMachineScheduler(this); if (Scheduler) return Scheduler; @@ -418,6 +499,37 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() { return createGenericSchedPostRA(this); } +bool PostMachineSchedulerImpl::run(MachineFunction &Func, + const TargetMachine &TM, + const RequiredAnalyses &Analyses) { + MF = &Func; + MLI = &Analyses.MLI; + this->TM = &TM; + AA = &Analyses.AA; + + if (VerifyScheduling) { + const char *PostMSchedBanner = "Before post machine scheduling."; + if (P) + MF->verify(P, PostMSchedBanner, &errs()); + else + MF->verify(*MFAM, PostMSchedBanner, &errs()); + } + + // Instantiate the selected scheduler for this target, function, and + // optimization level. + std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler()); + scheduleRegions(*Scheduler, true); + + if (VerifyScheduling) { + const char *PostMSchedBanner = "After post machine scheduling."; + if (P) + MF->verify(P, PostMSchedBanner, &errs()); + else + MF->verify(*MFAM, PostMSchedBanner, &errs()); + } + return true; +} + /// Top-level MachineScheduler pass driver. /// /// Visit blocks in function order. Divide each block into scheduling regions @@ -434,72 +546,112 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() { /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler /// design would be to split blocks at scheduling boundaries, but LLVM has a /// general bias against block splitting purely for implementation simplicity. -bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) { - if (skipFunction(mf.getFunction())) +bool MachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) { + if (skipFunction(MF.getFunction())) return false; if (EnableMachineSched.getNumOccurrences()) { if (!EnableMachineSched) return false; - } else if (!mf.getSubtarget().enableMachineScheduler()) + } else if (!MF.getSubtarget().enableMachineScheduler()) { return false; - - LLVM_DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs())); - - // Initialize the context of the pass. - MF = &mf; - MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI(); - MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(); - AA = &getAnalysis<AAResultsWrapperPass>().getAAResults(); - - LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS(); - - if (VerifyScheduling) { - LLVM_DEBUG(LIS->dump()); - MF->verify(this, "Before machine scheduling.", &errs()); } - RegClassInfo->runOnMachineFunction(*MF); - // Instantiate the selected scheduler for this target, function, and - // optimization level. - std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler()); - scheduleRegions(*Scheduler, false); + LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs())); - LLVM_DEBUG(LIS->dump()); - if (VerifyScheduling) - MF->verify(this, "After machine scheduling.", &errs()); - return true; + auto &MLI = getAnalysis<MachineLoopInfoWrapperPass>().getLI(); + auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(); + auto &TM = getAnalysis<TargetPassConfig>().getTM<TargetMachine>(); + auto &AA = getAnalysis<AAResultsWrapperPass>().getAAResults(); + auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS(); + Impl.setLegacyPass(this); + return Impl.run(MF, TM, {MLI, MDT, AA, LIS}); +} + +MachineSchedulerPass::MachineSchedulerPass(const TargetMachine *TM) + : Impl(std::make_unique<MachineSchedulerImpl>()), TM(TM) {} +MachineSchedulerPass::~MachineSchedulerPass() = default; +MachineSchedulerPass::MachineSchedulerPass(MachineSchedulerPass &&Other) = + default; + +PostMachineSchedulerPass::PostMachineSchedulerPass(const TargetMachine *TM) + : Impl(std::make_unique<PostMachineSchedulerImpl>()), TM(TM) {} +PostMachineSchedulerPass::PostMachineSchedulerPass( + PostMachineSchedulerPass &&Other) = default; +PostMachineSchedulerPass::~PostMachineSchedulerPass() = default; + +PreservedAnalyses +MachineSchedulerPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + if (EnableMachineSched.getNumOccurrences()) { + if (!EnableMachineSched) + return PreservedAnalyses::all(); + } else if (!MF.getSubtarget().enableMachineScheduler()) { + return PreservedAnalyses::all(); + } + + LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs())); + auto &MLI = MFAM.getResult<MachineLoopAnalysis>(MF); + auto &MDT = MFAM.getResult<MachineDominatorTreeAnalysis>(MF); + auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF) + .getManager(); + auto &AA = FAM.getResult<AAManager>(MF.getFunction()); + auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF); + Impl->setMFAM(&MFAM); + bool Changed = Impl->run(MF, *TM, {MLI, MDT, AA, LIS}); + if (!Changed) + return PreservedAnalyses::all(); + + PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses(); + PA.preserveSet<CFGAnalyses>(); + PA.preserve<SlotIndexesAnalysis>(); + PA.preserve<LiveIntervalsAnalysis>(); + return PA; } -bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) { - if (skipFunction(mf.getFunction())) +bool PostMachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) { + if (skipFunction(MF.getFunction())) return false; if (EnablePostRAMachineSched.getNumOccurrences()) { if (!EnablePostRAMachineSched) return false; - } else if (!mf.getSubtarget().enablePostRAMachineScheduler()) { + } else if (!MF.getSubtarget().enablePostRAMachineScheduler()) { LLVM_DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n"); return false; } - LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs())); - - // Initialize the context of the pass. - MF = &mf; - MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI(); - AA = &getAnalysis<AAResultsWrapperPass>().getAAResults(); - - if (VerifyScheduling) - MF->verify(this, "Before post machine scheduling.", &errs()); - - // Instantiate the selected scheduler for this target, function, and - // optimization level. - std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler()); - scheduleRegions(*Scheduler, true); + LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; MF.print(dbgs())); + auto &MLI = getAnalysis<MachineLoopInfoWrapperPass>().getLI(); + auto &TM = getAnalysis<TargetPassConfig>().getTM<TargetMachine>(); + auto &AA = getAnalysis<AAResultsWrapperPass>().getAAResults(); + Impl.setLegacyPass(this); + return Impl.run(MF, TM, {MLI, AA}); +} - if (VerifyScheduling) - MF->verify(this, "After post machine scheduling.", &errs()); - return true; +PreservedAnalyses +PostMachineSchedulerPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + if (EnablePostRAMachineSched.getNumOccurrences()) { + if (!EnablePostRAMachineSched) + return PreservedAnalyses::all(); + } else if (!MF.getSubtarget().enablePostRAMachineScheduler()) { + LLVM_DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n"); + return PreservedAnalyses::all(); + } + LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; MF.print(dbgs())); + auto &MLI = MFAM.getResult<MachineLoopAnalysis>(MF); + auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF) + .getManager(); + auto &AA = FAM.getResult<AAManager>(MF.getFunction()); + + Impl->setMFAM(&MFAM); + bool Changed = Impl->run(MF, *TM, {MLI, AA}); + if (!Changed) + return PreservedAnalyses::all(); + + PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses(); + PA.preserveSet<CFGAnalyses>(); + return PA; } /// Return true of the given instruction should not be included in a scheduling diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp index e1f0540..51e047b 100644 --- a/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -135,7 +135,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) INITIALIZE_PASS_DEPENDENCY(RegisterCoalescerLegacy) -INITIALIZE_PASS_DEPENDENCY(MachineScheduler) +INITIALIZE_PASS_DEPENDENCY(MachineSchedulerLegacy) INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 465c4e8..2e43ad7 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -155,7 +155,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) INITIALIZE_PASS_DEPENDENCY(RegisterCoalescerLegacy) -INITIALIZE_PASS_DEPENDENCY(MachineScheduler) +INITIALIZE_PASS_DEPENDENCY(MachineSchedulerLegacy) INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index e7ba721..650d23a 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -119,6 +119,7 @@ #include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/MachinePostDominators.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/MachineTraceMetrics.h" #include "llvm/CodeGen/MachineVerifier.h" #include "llvm/CodeGen/OptimizePHIs.h" diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 106a16f..7c0f104 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -71,6 +71,7 @@ #include "llvm/CodeGen/MIRParser/MIParser.h" #include "llvm/CodeGen/MachineCSE.h" #include "llvm/CodeGen/MachineLICM.h" +#include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/TargetPassConfig.h" @@ -1934,6 +1935,7 @@ AMDGPUCodeGenPassBuilder::AMDGPUCodeGenPassBuilder( GCNTargetMachine &TM, const CGPassBuilderOption &Opts, PassInstrumentationCallbacks *PIC) : CodeGenPassBuilder(TM, Opts, PIC) { + Opt.MISchedPostRA = true; Opt.RequiresCodeGenSCCOrder = true; // Exceptions and StackMaps are not supported, so these passes will never do // anything. diff --git a/llvm/test/CodeGen/AArch64/a55-fuse-address.mir b/llvm/test/CodeGen/AArch64/a55-fuse-address.mir index 4edff04..3e1b607 100644 --- a/llvm/test/CodeGen/AArch64/a55-fuse-address.mir +++ b/llvm/test/CodeGen/AArch64/a55-fuse-address.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -o - %s -mtriple=aarch64 -run-pass=machine-scheduler -verify-machineinstrs | FileCheck %s +# RUN: llc -o - %s -mtriple=aarch64 -passes=machine-scheduler | FileCheck %s --- | target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64" diff --git a/llvm/test/CodeGen/AArch64/ampere1-sched-add.mir b/llvm/test/CodeGen/AArch64/ampere1-sched-add.mir index e578b5d..3a33291 100644 --- a/llvm/test/CodeGen/AArch64/ampere1-sched-add.mir +++ b/llvm/test/CodeGen/AArch64/ampere1-sched-add.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 # RUN: llc -run-pass=machine-scheduler %s -o - | FileCheck %s +# RUN: llc -passes=machine-scheduler %s -o - | FileCheck %s --- | target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/cluster-frame-index.mir b/llvm/test/CodeGen/AArch64/cluster-frame-index.mir index 37ab941..5d761f1 100644 --- a/llvm/test/CodeGen/AArch64/cluster-frame-index.mir +++ b/llvm/test/CodeGen/AArch64/cluster-frame-index.mir @@ -1,4 +1,5 @@ #RUN: llc -mtriple=aarch64-- -mcpu=cyclone -run-pass machine-scheduler -o - %s | FileCheck %s +#RUN: llc -mtriple=aarch64-- -mcpu=cyclone -passes=machine-scheduler -o - %s | FileCheck %s --- name: merge_stack # CHECK-LABEL: name: merge_stack diff --git a/llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir b/llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir index 4bf8aff..5655bfa 100644 --- a/llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir +++ b/llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir @@ -1,9 +1,15 @@ # RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 -misched-dump-reserved-cycles=true \ # RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 -misched-dump-reserved-cycles=true \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s + # RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 -misched-dump-reserved-cycles=false\ # RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NODUMP +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 -misched-dump-reserved-cycles=false\ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NODUMP + # REQUIRES: asserts --- name: f diff --git a/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir b/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir index bff6d1d..c90d6bd 100644 --- a/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir +++ b/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir @@ -5,16 +5,33 @@ # RUN: 2>&1 | FileCheck %s --check-prefix=TOP --strict-whitespace # RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \ +# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \ +# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \ +# RUN: 2>&1 | FileCheck %s --check-prefix=TOP --strict-whitespace + +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \ # RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \ # RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \ # RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \ # RUN: 2>&1 | FileCheck %s --check-prefix=BOTTOM --strict-whitespace # RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \ +# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \ +# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \ +# RUN: 2>&1 | FileCheck %s --check-prefix=BOTTOM --strict-whitespace + +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \ # RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \ # RUN: -sched-print-cycles=true -misched-dump-schedule-trace=true \ # RUN: 2>&1 | FileCheck %s --check-prefix=BIDIRECTIONAL +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \ +# RUN: -sched-print-cycles=true -misched-dump-schedule-trace=true \ +# RUN: 2>&1 | FileCheck %s --check-prefix=BIDIRECTIONAL + # REQUIRES: asserts, aarch64-registered-target --- name: f diff --git a/llvm/test/CodeGen/AArch64/force-enable-intervals.mir b/llvm/test/CodeGen/AArch64/force-enable-intervals.mir index a53d4e7..8d47eee 100644 --- a/llvm/test/CodeGen/AArch64/force-enable-intervals.mir +++ b/llvm/test/CodeGen/AArch64/force-enable-intervals.mir @@ -4,10 +4,20 @@ # RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s # RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \ +# RUN: -misched-dump-reserved-cycles=true \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler \ +# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s + +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \ # RUN: -misched-dump-reserved-cycles=true -sched-model-force-enable-intervals=true \ # RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \ # RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s --check-prefix=FORCE +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \ +# RUN: -misched-dump-reserved-cycles=true -sched-model-force-enable-intervals=true \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler \ +# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s --check-prefix=FORCE + # REQUIRES: asserts, aarch64-registered-target --- name: f diff --git a/llvm/test/CodeGen/AArch64/machine-scheduler.mir b/llvm/test/CodeGen/AArch64/machine-scheduler.mir index 6c0222f..ba2c2b3 100644 --- a/llvm/test/CodeGen/AArch64/machine-scheduler.mir +++ b/llvm/test/CodeGen/AArch64/machine-scheduler.mir @@ -1,4 +1,5 @@ # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-scheduler -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=aarch64-none-linux-gnu -passes=machine-scheduler -o - %s | FileCheck %s --- | define i64 @load_imp-def(ptr nocapture %P, i32 %v) { diff --git a/llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir b/llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir index 8c5a85a..2f0d19f 100644 --- a/llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir +++ b/llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir @@ -1,5 +1,7 @@ # RUN: llc -o - %s -mtriple=aarch64-- -mattr=+fuse-addsub-2reg-const1 -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,FUSION +# RUN: llc -o - %s -mtriple=aarch64-- -mattr=+fuse-addsub-2reg-const1 -passes=postmisched | FileCheck %s --check-prefixes=CHECK,FUSION # RUN: llc -o - %s -mtriple=aarch64-- -mattr=-fuse-addsub-2reg-const1 -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,NOFUSION +# RUN: llc -o - %s -mtriple=aarch64-- -mattr=-fuse-addsub-2reg-const1 -passes=postmisched | FileCheck %s --check-prefixes=CHECK,NOFUSION --- # CHECK-LABEL: name: addsub2reg # CHECK: $w8 = ADDWrr killed renamable $w0, killed renamable $w1 diff --git a/llvm/test/CodeGen/AArch64/macro-fusion-last.mir b/llvm/test/CodeGen/AArch64/macro-fusion-last.mir index 14937a4..affd2bb 100644 --- a/llvm/test/CodeGen/AArch64/macro-fusion-last.mir +++ b/llvm/test/CodeGen/AArch64/macro-fusion-last.mir @@ -1,5 +1,7 @@ # RUN: llc -o - %s -mtriple=aarch64-- -mattr=+arith-bcc-fusion -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,FUSION +# RUN: llc -o - %s -mtriple=aarch64-- -mattr=+arith-bcc-fusion -passes=postmisched | FileCheck %s --check-prefixes=CHECK,FUSION # RUN: llc -o - %s -mtriple=aarch64-- -mattr=-arith-bcc-fusion -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,NOFUSION +# RUN: llc -o - %s -mtriple=aarch64-- -mattr=-arith-bcc-fusion -passes=postmisched | FileCheck %s --check-prefixes=CHECK,NOFUSION # Make sure the last instruction is correctly macro-fused when scheduling # top-down (post-ra). --- diff --git a/llvm/test/CodeGen/AArch64/misched-branch-targets.mir b/llvm/test/CodeGen/AArch64/misched-branch-targets.mir index 40f1484..9540826 100644 --- a/llvm/test/CodeGen/AArch64/misched-branch-targets.mir +++ b/llvm/test/CodeGen/AArch64/misched-branch-targets.mir @@ -1,6 +1,9 @@ # RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s # RUN: llc -o - -run-pass=postmisched %s | FileCheck %s +# RUN: llc -o - -passes=machine-scheduler -misched=shuffle %s | FileCheck %s +# RUN: llc -o - -passes=postmisched %s | FileCheck %s + # REQUIRES: asserts # -misched=shuffle is only available with assertions enabled diff --git a/llvm/test/CodeGen/AArch64/misched-bundle.mir b/llvm/test/CodeGen/AArch64/misched-bundle.mir index ac6112e..8463cb0 100644 --- a/llvm/test/CodeGen/AArch64/misched-bundle.mir +++ b/llvm/test/CodeGen/AArch64/misched-bundle.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 # RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a510 -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a510 -passes=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s # REQUIRES: asserts # CHECK: SU(0): renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size, align 1) diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir index ea40f9e..ca92fa1 100644 --- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir +++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir @@ -6,6 +6,14 @@ # RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \ # RUN: | FileCheck %s +# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -mcpu=cortex-a55 %s -o - 2>&1 \ +# RUN: -misched-dump-reserved-cycles=true \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler \ +# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \ +# RUN: -misched-detail-resource-booking=true \ +# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \ +# RUN: | FileCheck %s + # REQUIRES: asserts, aarch64-registered-target --- | diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir index 9be91b8..2b34ca5 100644 --- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir +++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir @@ -5,6 +5,13 @@ # RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \ # RUN: 2>&1 | FileCheck %s +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \ +# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \ +# RUN: -misched-dump-reserved-cycles=true -misched-detail-resource-booking=true\ +# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \ +# RUN: 2>&1 | FileCheck %s + # REQUIRES: asserts, aarch64-registered-target --- name: f diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir b/llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir index 6227677..60c0026 100644 --- a/llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir +++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir @@ -1,5 +1,7 @@ # RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mattr=fuse-arith-logic -run-pass=machine-scheduler -misched-print-dags | FileCheck %s +# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mattr=fuse-arith-logic -passes=machine-scheduler -misched-print-dags | FileCheck %s # RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=exynos-m4 -run-pass=machine-scheduler -misched-print-dags | FileCheck %s +# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=exynos-m4 -passes=machine-scheduler -misched-print-dags | FileCheck %s # REQUIRES: asserts --- diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir b/llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir index b0450c5..8249816 100644 --- a/llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir +++ b/llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir @@ -1,4 +1,5 @@ # RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=cortex-x1 -run-pass=machine-scheduler +# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=cortex-x1 -passes=machine-scheduler # Just ensure this doesn't crash. --- diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir b/llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir index 623a822..e661353 100644 --- a/llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir +++ b/llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir @@ -1,6 +1,9 @@ # RUN: llc -o /dev/null %s -run-pass=machine-scheduler -mtriple aarch64-- -mattr=-fuse-aes,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,NOFUSE # RUN: llc -o /dev/null %s -run-pass=machine-scheduler -mtriple aarch64-- -mattr=+fuse-aes,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSEAES # RUN: llc -o /dev/null %s -run-pass=machine-scheduler -mtriple aarch64-- -mattr=+fuse-aes,+fuse-crypto-eor,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSEAES,FUSECRYPTO +# RUN: llc -o /dev/null %s -passes=machine-scheduler -mtriple aarch64-- -mattr=-fuse-aes,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,NOFUSE +# RUN: llc -o /dev/null %s -passes=machine-scheduler -mtriple aarch64-- -mattr=+fuse-aes,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSEAES +# RUN: llc -o /dev/null %s -passes=machine-scheduler -mtriple aarch64-- -mattr=+fuse-aes,+fuse-crypto-eor,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSEAES,FUSECRYPTO # REQUIRES: asserts name: func diff --git a/llvm/test/CodeGen/AArch64/misched-move-imm.mir b/llvm/test/CodeGen/AArch64/misched-move-imm.mir index b5ff01b..65608bb 100644 --- a/llvm/test/CodeGen/AArch64/misched-move-imm.mir +++ b/llvm/test/CodeGen/AArch64/misched-move-imm.mir @@ -1,4 +1,5 @@ # RUN: llc -run-pass=machine-scheduler -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 %s -o /dev/null 2>&1 +# RUN: llc -passes=machine-scheduler -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 %s -o /dev/null 2>&1 # Just ensure this doesn't crash. Ensures in the neoverse-v2 # scheduling model we don't attempt to treat the first input # operand of MOVZXi as an immediate operand. diff --git a/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir b/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir index 0b14cee..17a6cf7 100644 --- a/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir +++ b/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir @@ -1,4 +1,5 @@ # RUN: llc -mcpu=exynos-m5 -mtriple=aarch64 -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o /dev/null 2>&1 | FileCheck %s +# RUN: llc -mcpu=exynos-m5 -mtriple=aarch64 -enable-misched -passes=machine-scheduler -debug-only=machine-scheduler %s -o /dev/null 2>&1 | FileCheck %s # REQUIRES: asserts # CHECK-LABEL: ********** MI Scheduling ********** diff --git a/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir b/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir index b04fd89b..b652d24 100644 --- a/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir +++ b/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir @@ -4,10 +4,20 @@ # RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=true 2>&1 | FileCheck --check-prefix=SORTED %s # RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \ +# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \ +# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=true 2>&1 | FileCheck --check-prefix=SORTED %s + +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \ # RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \ # RUN: -misched-prera-direction=topdown -sched-print-cycles=true \ # RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=false 2>&1 | FileCheck --check-prefix=UNSORTED %s +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \ +# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \ +# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=false 2>&1 | FileCheck --check-prefix=UNSORTED %s + # REQUIRES: asserts, aarch64-registered-target --- name: test diff --git a/llvm/test/CodeGen/AArch64/sched-postidxalias.mir b/llvm/test/CodeGen/AArch64/sched-postidxalias.mir index 98ee0fa..02256ca 100644 --- a/llvm/test/CodeGen/AArch64/sched-postidxalias.mir +++ b/llvm/test/CodeGen/AArch64/sched-postidxalias.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 # RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s # REQUIRES: asserts # Both the accesses should have an offset of 0 diff --git a/llvm/test/CodeGen/AArch64/sched-print-cycle.mir b/llvm/test/CodeGen/AArch64/sched-print-cycle.mir index 59c5157..d58037e 100644 --- a/llvm/test/CodeGen/AArch64/sched-print-cycle.mir +++ b/llvm/test/CodeGen/AArch64/sched-print-cycle.mir @@ -1,9 +1,15 @@ # RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=true \ # RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=true \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s + # RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=false \ # RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NOCYCLES +# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=false \ +# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NOCYCLES + # REQUIRES: asserts --- name: mul_mul diff --git a/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir b/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir index 65ec434..66680af 100644 --- a/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir +++ b/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir @@ -1,4 +1,5 @@ # RUN: llc -o /dev/null %s -mtriple=aarch64-- -run-pass=machine-scheduler -enable-misched -debug-only=machine-scheduler 2>&1 | FileCheck %s +# RUN: llc -o /dev/null %s -mtriple=aarch64-- -passes=machine-scheduler -enable-misched -debug-only=machine-scheduler 2>&1 | FileCheck %s # REQUIRES: asserts --- | define void @func() { ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-aliasing.mir b/llvm/test/CodeGen/AArch64/sve-aliasing.mir index 3b7c9fe..34a08ad 100644 --- a/llvm/test/CodeGen/AArch64/sve-aliasing.mir +++ b/llvm/test/CodeGen/AArch64/sve-aliasing.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -o - %s -mtriple=aarch64 -run-pass=machine-scheduler -verify-machineinstrs | FileCheck %s +# RUN: llc -o - %s -mtriple=aarch64 -passes=machine-scheduler | FileCheck %s --- name: scalable_v16i1 diff --git a/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir b/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir index 82ee173..1c4093b 100644 --- a/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir +++ b/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir @@ -1,5 +1,7 @@ # RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=machine-scheduler -verify-misched -o /dev/null %s 2>&1 | FileCheck %s + # CHECK: *** Bad machine code: No live subrange at use *** # CHECK-NEXT: - function: at_least_one_value_should_be_defined_by_this_mask # CHECK-NEXT: - basic block: %bb.0 diff --git a/llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir b/llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir index 0d84dc0..1ae544f 100644 --- a/llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir +++ b/llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir @@ -1,4 +1,5 @@ # RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass machine-scheduler %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=machine-scheduler %s -o - | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: cluster_flat_loads # GCN: FLAT_LOAD_DWORD %0, 0 diff --git a/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir b/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir index 4945c70..b38dc4d 100644 --- a/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir +++ b/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=machine-scheduler -o - %s | FileCheck %s # The DBG_VALUE in bb.5 ends a scheduling region, and its uses should # not be tracked like a normal instruction. diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir index 8a1c68b..156979d 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir +++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=machine-scheduler %s -o - | FileCheck %s --- | declare void @llvm.dbg.value(metadata, metadata, metadata) #0 diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir index 19071be..d415346 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir +++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir @@ -1,4 +1,5 @@ # RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s # REQUIRES: asserts # CHECK: ********** MI Scheduling ********** diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir index 4f15e0e..170672d 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir +++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir @@ -1,4 +1,5 @@ # RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s # REQUIRES: asserts # CHECK: All regions recorded, starting actual scheduling. diff --git a/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir b/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir index 962d49d..204912b 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir +++ b/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir @@ -1,4 +1,5 @@ # RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=tonga -passes=machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: flat_load_clustering # GCN: FLAT_LOAD_DWORD diff --git a/llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir b/llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir index d57450b..78f21ef 100644 --- a/llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir +++ b/llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir @@ -1,6 +1,8 @@ # REQUIRES: asserts -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -run-pass=machine-scheduler -verify-misched -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -run-pass=machine-scheduler -amdgpu-use-amdgpu-trackers=1 -verify-misched -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN-GCNTRACKER %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -run-pass=machine-scheduler -amdgpu-use-amdgpu-trackers=1 -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN-GCNTRACKER %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -passes=machine-scheduler -amdgpu-use-amdgpu-trackers=1 -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN-GCNTRACKER %s --- | define amdgpu_kernel void @high-RP-reschedule() { ret void } diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir index e32de1e..5dc6d2e 100644 --- a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir +++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir @@ -1,4 +1,5 @@ # RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass machine-scheduler -amdgpu-disable-unclustered-high-rp-reschedule -verify-machineinstrs %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck -check-prefix=DEBUG %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler -amdgpu-disable-unclustered-high-rp-reschedule %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck -check-prefix=DEBUG %s # REQUIRES: asserts --- | diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir index fb65d80..9991cb18 100644 --- a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir +++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler -amdgpu-disable-unclustered-high-rp-reschedule -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX908 %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler -amdgpu-disable-unclustered-high-rp-reschedule %s -o - | FileCheck -check-prefix=GFX908 %s --- name: test_occ_10_max_occ_no_sink diff --git a/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir b/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir index 2aa4304..ffc86dc 100644 --- a/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir +++ b/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir @@ -1,4 +1,5 @@ # RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn -mcpu=tahiti -passes=machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: cluster_add_addc # GCN: S_NOP 0, implicit-def $vcc diff --git a/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir b/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir index c933fb0..c909759 100644 --- a/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir +++ b/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=machine-scheduler -verify-misched -o - %s | FileCheck %s # This would assert that a dead def should have no uses, but the dead # def and use have different subreg indices. diff --git a/llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir b/llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir index add7825..2cd7806 100644 --- a/llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir +++ b/llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=machine-scheduler %s -o - | FileCheck %s # The sequence of DBG_VALUEs forms a scheduling region with 0 real # instructions. The RegPressure tracker would end up skipping over any diff --git a/llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir b/llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir index 3fdb0c7..f797b01 100644 --- a/llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir +++ b/llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler -verify-misched -o - %s | FileCheck %s # This would hang after removing edges from the SCHED_BARRIER since the number # of Preds/Succs would be left in an inconsistent state. diff --git a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir index 0903770..3254f5e 100644 --- a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir +++ b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir @@ -1,4 +1,5 @@ # RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -passes=machine-scheduler -o - %s | FileCheck %s --- | %struct.widget.0 = type { float, i32, i32 } diff --git a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir index 6796391..3ca61d2 100644 --- a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir +++ b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -verify-misched -run-pass=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-misched -passes=machine-scheduler -o - %s | FileCheck %s --- name: handleMoveUp_incorrect_interval diff --git a/llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir b/llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir index 0b1fd44..099cfc4 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir +++ b/llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir @@ -1,6 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -passes=machine-scheduler -o - %s | FileCheck %s # RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=machine-scheduler -o - %s | FileCheck %s # Make sure FP mode is not a hard scheduling boundary --- diff --git a/llvm/test/CodeGen/AMDGPU/schedule-barrier.mir b/llvm/test/CodeGen/AMDGPU/schedule-barrier.mir index e67036f..88e11c9 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-barrier.mir +++ b/llvm/test/CodeGen/AMDGPU/schedule-barrier.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=machine-scheduler -o - %s | FileCheck %s --- # Check that the high latency loads are both scheduled first, before the diff --git a/llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir b/llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir index d8d4f5d..3091fe8 100644 --- a/llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir +++ b/llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=postmisched -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=postmisched -o - %s | FileCheck %s --- name: test_xnull_256 body: | diff --git a/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir b/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir index 0a47b87..1bee32f 100644 --- a/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir +++ b/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple arm-arm-eabi -mcpu=cortex-m7 -verify-machineinstrs -run-pass=postmisched %s -o - | FileCheck %s +# RUN: llc -mtriple arm-arm-eabi -mcpu=cortex-m7 -passes=postmisched %s -o - | FileCheck %s --- name: test_groups alignment: 2 diff --git a/llvm/test/CodeGen/ARM/misched-branch-targets.mir b/llvm/test/CodeGen/ARM/misched-branch-targets.mir index d828d9e..610344f 100644 --- a/llvm/test/CodeGen/ARM/misched-branch-targets.mir +++ b/llvm/test/CodeGen/ARM/misched-branch-targets.mir @@ -1,5 +1,7 @@ # RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s +# RUN: llc -o - -passes=machine-scheduler -misched=shuffle %s | FileCheck %s # RUN: llc -o - -run-pass=postmisched %s | FileCheck %s +# RUN: llc -o - -passes=postmisched %s | FileCheck %s # REQUIRES: asserts # -misched=shuffle is only available with assertions enabled diff --git a/llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir b/llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir index 627e553..8bdbe28 100644 --- a/llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir +++ b/llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=postmisched -o - %s | FileCheck %s +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -passes=postmisched -o - %s | FileCheck %s --- # Check that postmisched's TopDepthReduce heuristic moves the MULLD later # because of the dependency on x5 diff --git a/llvm/test/CodeGen/RISCV/misched-postra-direction.mir b/llvm/test/CodeGen/RISCV/misched-postra-direction.mir index 2cca042..e4b934c 100644 --- a/llvm/test/CodeGen/RISCV/misched-postra-direction.mir +++ b/llvm/test/CodeGen/RISCV/misched-postra-direction.mir @@ -11,6 +11,19 @@ # RUN: -misched-dump-schedule-trace -misched-postra-direction=bidirectional \ # RUN: -o - %s 2>&1 | FileCheck --check-prefix=BIDIRECTIONAL %s +# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -passes=postmisched \ +# RUN: -enable-post-misched -debug-only=machine-scheduler \ +# RUN: -misched-dump-schedule-trace -misched-postra-direction=topdown \ +# RUN: -o - %s 2>&1 | FileCheck --check-prefix=TOPDOWN %s +# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -passes=postmisched \ +# RUN: -enable-post-misched -debug-only=machine-scheduler \ +# RUN: -misched-dump-schedule-trace -misched-postra-direction=bottomup \ +# RUN: -o - %s 2>&1 | FileCheck --check-prefix=BOTTOMUP %s +# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -passes=postmisched \ +# RUN: -enable-post-misched -debug-only=machine-scheduler \ +# RUN: -misched-dump-schedule-trace -misched-postra-direction=bidirectional \ +# RUN: -o - %s 2>&1 | FileCheck --check-prefix=BIDIRECTIONAL %s + # REQUIRES: asserts --- |