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-rw-r--r--llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 129b4cb..caa5dbc1 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -72,7 +72,8 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
}
bool HasVectorCSR =
- MF->getFunction().getCallingConv() == CallingConv::RISCV_VectorCall;
+ MF->getFunction().getCallingConv() == CallingConv::RISCV_VectorCall &&
+ Subtarget.hasVInstructions();
switch (Subtarget.getTargetABI()) {
default: