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-rw-r--r--llvm/test/CodeGen/AArch64/arm64-ext.ll65
-rw-r--r--llvm/test/CodeGen/AArch64/arm64-neon-copy.ll20
-rw-r--r--llvm/test/CodeGen/AArch64/arm64-vext.ll250
-rw-r--r--llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll131
-rw-r--r--llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll159
-rw-r--r--llvm/test/CodeGen/AArch64/lifetime-poison.ll14
-rw-r--r--llvm/test/CodeGen/RISCV/xqcilsm-memset.ll900
-rw-r--r--llvm/test/Instrumentation/AddressSanitizer/lifetime.ll15
-rw-r--r--llvm/test/Instrumentation/HWAddressSanitizer/stack-safety-analysis.ll19
-rw-r--r--llvm/test/MC/ELF/many-instructions.s10
-rw-r--r--llvm/test/MC/ELF/mc-dump.s2
-rw-r--r--llvm/test/Transforms/InstCombine/pr150338.ll16
-rw-r--r--llvm/test/Transforms/InstCombine/unreachable-alloca-lifetime-markers.ll51
-rw-r--r--llvm/test/tools/llvm-reduce/reduce-operands-alloca.ll12
14 files changed, 1487 insertions, 177 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-ext.ll b/llvm/test/CodeGen/AArch64/arm64-ext.ll
index 50df6a0..8bf2b82 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ext.ll
@@ -135,3 +135,68 @@ define <2 x ptr> @test_v2p0(<2 x ptr> %a, <2 x ptr> %b) {
%s = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 3, i32 0>
ret <2 x ptr> %s
}
+
+define <16 x i8> @reverse_vector_s8x16b(<16 x i8> noundef %x) {
+; CHECK-SD-LABEL: reverse_vector_s8x16b:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: rev64 v1.16b, v0.16b
+; CHECK-SD-NEXT: ext v0.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: reverse_vector_s8x16b:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: rev64 v1.16b, v0.16b
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ret
+entry:
+ %shuffle.i = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
+ %shuffle.i6 = shufflevector <16 x i8> %shuffle.i, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %shuffle.i7 = shufflevector <16 x i8> %shuffle.i, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %shuffle.i5 = shufflevector <8 x i8> %shuffle.i6, <8 x i8> %shuffle.i7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %shuffle.i5
+}
+
+define <8 x i16> @reverse_vector_s16x8b(<8 x i16> noundef %x) {
+; CHECK-SD-LABEL: reverse_vector_s16x8b:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: rev64 v1.8h, v0.8h
+; CHECK-SD-NEXT: ext v0.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: reverse_vector_s16x8b:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: rev64 v1.8h, v0.8h
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ret
+entry:
+ %shuffle.i = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+ %shuffle.i6 = shufflevector <8 x i16> %shuffle.i, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %shuffle.i7 = shufflevector <8 x i16> %shuffle.i, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ %shuffle.i5 = shufflevector <4 x i16> %shuffle.i6, <4 x i16> %shuffle.i7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %shuffle.i5
+}
+
+define <4 x i32> @reverse_vector_s32x4b(<4 x i32> noundef %x) {
+; CHECK-SD-LABEL: reverse_vector_s32x4b:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: reverse_vector_s32x4b:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: rev64 v1.4s, v0.4s
+; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ret
+entry:
+ %shuffle.i = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+ %shuffle.i6 = shufflevector <4 x i32> %shuffle.i, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
+ %shuffle.i7 = shufflevector <4 x i32> %shuffle.i, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
+ %shuffle.i5 = shufflevector <2 x i32> %shuffle.i6, <2 x i32> %shuffle.i7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %shuffle.i5
+}
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index 367105f7..f4e59fe 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -1708,7 +1708,7 @@ define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {
; CHECK-GI-LABEL: test_concat_v16i8_v8i8_v16i8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v2.16b, v1.16b
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0
; CHECK-GI-NEXT: adrp x8, .LCPI127_0
; CHECK-GI-NEXT: mov v1.b[0], v0.b[0]
; CHECK-GI-NEXT: mov v1.b[1], v0.b[1]
@@ -1752,7 +1752,7 @@ define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 {
; CHECK-GI-LABEL: test_concat_v16i8_v16i8_v8i8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov b2, v0.b[0]
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1
; CHECK-GI-NEXT: mov v2.b[1], v0.b[1]
; CHECK-GI-NEXT: mov v2.b[2], v0.b[2]
; CHECK-GI-NEXT: mov v2.b[3], v0.b[3]
@@ -1816,9 +1816,9 @@ define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 {
;
; CHECK-GI-LABEL: test_concat_v16i8_v8i8_v8i8:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0 def $q0
; CHECK-GI-NEXT: mov v2.b[0], v0.b[0]
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1 def $q1
; CHECK-GI-NEXT: mov v2.b[1], v0.b[1]
; CHECK-GI-NEXT: mov v2.b[2], v0.b[2]
; CHECK-GI-NEXT: mov v2.b[3], v0.b[3]
@@ -1901,7 +1901,7 @@ define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {
; CHECK-GI-LABEL: test_concat_v8i16_v4i16_v8i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v2.16b, v1.16b
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 def $q0 def $q0 def $q0
; CHECK-GI-NEXT: adrp x8, .LCPI131_0
; CHECK-GI-NEXT: mov v1.h[0], v0.h[0]
; CHECK-GI-NEXT: mov v1.h[1], v0.h[1]
@@ -1933,7 +1933,7 @@ define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 {
; CHECK-GI-LABEL: test_concat_v8i16_v8i16_v4i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov h2, v0.h[0]
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 def $q1 def $q1 def $q1
; CHECK-GI-NEXT: mov v2.h[1], v0.h[1]
; CHECK-GI-NEXT: mov v2.h[2], v0.h[2]
; CHECK-GI-NEXT: mov v2.h[3], v0.h[3]
@@ -1973,9 +1973,9 @@ define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 {
;
; CHECK-GI-LABEL: test_concat_v8i16_v4i16_v4i16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 def $q0 def $q0 def $q0
; CHECK-GI-NEXT: mov v2.h[0], v0.h[0]
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 def $q1 def $q1 def $q1
; CHECK-GI-NEXT: mov v2.h[1], v0.h[1]
; CHECK-GI-NEXT: mov v2.h[2], v0.h[2]
; CHECK-GI-NEXT: mov v2.h[3], v0.h[3]
@@ -2034,7 +2034,7 @@ define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {
; CHECK-GI-LABEL: test_concat_v4i32_v2i32_v4i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov v2.16b, v1.16b
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 def $q0
; CHECK-GI-NEXT: adrp x8, .LCPI135_0
; CHECK-GI-NEXT: mov v1.s[0], v0.s[0]
; CHECK-GI-NEXT: mov v1.s[1], v0.s[1]
@@ -2060,7 +2060,7 @@ define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 {
; CHECK-GI-LABEL: test_concat_v4i32_v4i32_v2i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov s2, v0.s[0]
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 def $q1
; CHECK-GI-NEXT: mov v2.s[1], v0.s[1]
; CHECK-GI-NEXT: mov v2.s[2], v1.s[0]
; CHECK-GI-NEXT: mov v2.s[3], v1.s[1]
diff --git a/llvm/test/CodeGen/AArch64/arm64-vext.ll b/llvm/test/CodeGen/AArch64/arm64-vext.ll
index a56bd6b..e522c05 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vext.ll
@@ -1,8 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define void @test_vext_s8() nounwind ssp {
- ; CHECK-LABEL: test_vext_s8:
- ; CHECK: {{ext.8.*#1}}
+; CHECK-LABEL: test_vext_s8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #1
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xS8x8 = alloca <8 x i8>, align 8
%__a = alloca <8 x i8>, align 8
%__b = alloca <8 x i8>, align 8
@@ -18,8 +26,15 @@ define void @test_vext_s8() nounwind ssp {
}
define void @test_vext_u8() nounwind ssp {
- ; CHECK-LABEL: test_vext_u8:
- ; CHECK: {{ext.8.*#2}}
+; CHECK-LABEL: test_vext_u8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #2
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xU8x8 = alloca <8 x i8>, align 8
%__a = alloca <8 x i8>, align 8
%__b = alloca <8 x i8>, align 8
@@ -35,8 +50,15 @@ define void @test_vext_u8() nounwind ssp {
}
define void @test_vext_p8() nounwind ssp {
- ; CHECK-LABEL: test_vext_p8:
- ; CHECK: {{ext.8.*#3}}
+; CHECK-LABEL: test_vext_p8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #3
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xP8x8 = alloca <8 x i8>, align 8
%__a = alloca <8 x i8>, align 8
%__b = alloca <8 x i8>, align 8
@@ -52,8 +74,15 @@ define void @test_vext_p8() nounwind ssp {
}
define void @test_vext_s16() nounwind ssp {
- ; CHECK-LABEL: test_vext_s16:
- ; CHECK: {{ext.8.*#2}}
+; CHECK-LABEL: test_vext_s16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #2
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xS16x4 = alloca <4 x i16>, align 8
%__a = alloca <4 x i16>, align 8
%__b = alloca <4 x i16>, align 8
@@ -73,8 +102,15 @@ define void @test_vext_s16() nounwind ssp {
}
define void @test_vext_u16() nounwind ssp {
- ; CHECK-LABEL: test_vext_u16:
- ; CHECK: {{ext.8.*#4}}
+; CHECK-LABEL: test_vext_u16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #4
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xU16x4 = alloca <4 x i16>, align 8
%__a = alloca <4 x i16>, align 8
%__b = alloca <4 x i16>, align 8
@@ -94,8 +130,15 @@ define void @test_vext_u16() nounwind ssp {
}
define void @test_vext_p16() nounwind ssp {
- ; CHECK-LABEL: test_vext_p16:
- ; CHECK: {{ext.8.*#6}}
+; CHECK-LABEL: test_vext_p16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: ext.8b v1, v0, v0, #6
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xP16x4 = alloca <4 x i16>, align 8
%__a = alloca <4 x i16>, align 8
%__b = alloca <4 x i16>, align 8
@@ -115,8 +158,15 @@ define void @test_vext_p16() nounwind ssp {
}
define void @test_vext_s32() nounwind ssp {
- ; CHECK-LABEL: test_vext_s32:
- ; CHECK: {{rev64.2s.*}}
+; CHECK-LABEL: test_vext_s32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: rev64.2s v1, v0
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xS32x2 = alloca <2 x i32>, align 8
%__a = alloca <2 x i32>, align 8
%__b = alloca <2 x i32>, align 8
@@ -136,8 +186,15 @@ define void @test_vext_s32() nounwind ssp {
}
define void @test_vext_u32() nounwind ssp {
- ; CHECK-LABEL: test_vext_u32:
- ; CHECK: {{rev64.2s.*}}
+; CHECK-LABEL: test_vext_u32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: rev64.2s v1, v0
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xU32x2 = alloca <2 x i32>, align 8
%__a = alloca <2 x i32>, align 8
%__b = alloca <2 x i32>, align 8
@@ -157,8 +214,15 @@ define void @test_vext_u32() nounwind ssp {
}
define void @test_vext_f32() nounwind ssp {
- ; CHECK-LABEL: test_vext_f32:
- ; CHECK: {{rev64.2s.*}}
+; CHECK-LABEL: test_vext_f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: rev64.2s v1, v0
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: str d1, [sp, #24]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%xF32x2 = alloca <2 x float>, align 8
%__a = alloca <2 x float>, align 8
%__b = alloca <2 x float>, align 8
@@ -178,7 +242,13 @@ define void @test_vext_f32() nounwind ssp {
}
define void @test_vext_s64() nounwind ssp {
- ; CHECK-LABEL: test_vext_s64:
+; CHECK-LABEL: test_vext_s64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
; CHECK_FIXME: {{rev64.2s.*}}
; this just turns into a load of the second element
%xS64x1 = alloca <1 x i64>, align 8
@@ -200,7 +270,13 @@ define void @test_vext_s64() nounwind ssp {
}
define void @test_vext_u64() nounwind ssp {
- ; CHECK-LABEL: test_vext_u64:
+; CHECK-LABEL: test_vext_u64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: ldr d0, [sp, #24]
+; CHECK-NEXT: stp d0, d0, [sp, #8]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
; CHECK_FIXME: {{ext.8.*#1}}
; this is turned into a simple load of the 2nd element
%xU64x1 = alloca <1 x i64>, align 8
@@ -222,8 +298,15 @@ define void @test_vext_u64() nounwind ssp {
}
define void @test_vextq_s8() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s8:
- ; CHECK: {{ext.16.*#4}}
+; CHECK-LABEL: test_vextq_s8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #4
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xS8x16 = alloca <16 x i8>, align 16
%__a = alloca <16 x i8>, align 16
%__b = alloca <16 x i8>, align 16
@@ -239,8 +322,15 @@ define void @test_vextq_s8() nounwind ssp {
}
define void @test_vextq_u8() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u8:
- ; CHECK: {{ext.16.*#5}}
+; CHECK-LABEL: test_vextq_u8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #5
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xU8x16 = alloca <16 x i8>, align 16
%__a = alloca <16 x i8>, align 16
%__b = alloca <16 x i8>, align 16
@@ -256,8 +346,15 @@ define void @test_vextq_u8() nounwind ssp {
}
define void @test_vextq_p8() nounwind ssp {
- ; CHECK-LABEL: test_vextq_p8:
- ; CHECK: {{ext.16.*#6}}
+; CHECK-LABEL: test_vextq_p8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #6
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xP8x16 = alloca <16 x i8>, align 16
%__a = alloca <16 x i8>, align 16
%__b = alloca <16 x i8>, align 16
@@ -273,8 +370,15 @@ define void @test_vextq_p8() nounwind ssp {
}
define void @test_vextq_s16() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s16:
- ; CHECK: {{ext.16.*#14}}
+; CHECK-LABEL: test_vextq_s16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #14
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xS16x8 = alloca <8 x i16>, align 16
%__a = alloca <8 x i16>, align 16
%__b = alloca <8 x i16>, align 16
@@ -294,8 +398,15 @@ define void @test_vextq_s16() nounwind ssp {
}
define void @test_vextq_u16() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u16:
- ; CHECK: {{ext.16.*#8}}
+; CHECK-LABEL: test_vextq_u16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #8
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xU16x8 = alloca <8 x i16>, align 16
%__a = alloca <8 x i16>, align 16
%__b = alloca <8 x i16>, align 16
@@ -315,8 +426,15 @@ define void @test_vextq_u16() nounwind ssp {
}
define void @test_vextq_p16() nounwind ssp {
- ; CHECK-LABEL: test_vextq_p16:
- ; CHECK: {{ext.16.*#10}}
+; CHECK-LABEL: test_vextq_p16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #10
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xP16x8 = alloca <8 x i16>, align 16
%__a = alloca <8 x i16>, align 16
%__b = alloca <8 x i16>, align 16
@@ -336,8 +454,15 @@ define void @test_vextq_p16() nounwind ssp {
}
define void @test_vextq_s32() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s32:
- ; CHECK: {{ext.16.*#4}}
+; CHECK-LABEL: test_vextq_s32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #4
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xS32x4 = alloca <4 x i32>, align 16
%__a = alloca <4 x i32>, align 16
%__b = alloca <4 x i32>, align 16
@@ -357,8 +482,15 @@ define void @test_vextq_s32() nounwind ssp {
}
define void @test_vextq_u32() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u32:
- ; CHECK: {{ext.16.*#8}}
+; CHECK-LABEL: test_vextq_u32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #8
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xU32x4 = alloca <4 x i32>, align 16
%__a = alloca <4 x i32>, align 16
%__b = alloca <4 x i32>, align 16
@@ -378,8 +510,15 @@ define void @test_vextq_u32() nounwind ssp {
}
define void @test_vextq_f32() nounwind ssp {
- ; CHECK-LABEL: test_vextq_f32:
- ; CHECK: {{ext.16.*#12}}
+; CHECK-LABEL: test_vextq_f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #12
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xF32x4 = alloca <4 x float>, align 16
%__a = alloca <4 x float>, align 16
%__b = alloca <4 x float>, align 16
@@ -399,8 +538,15 @@ define void @test_vextq_f32() nounwind ssp {
}
define void @test_vextq_s64() nounwind ssp {
- ; CHECK-LABEL: test_vextq_s64:
- ; CHECK: {{ext.16.*#8}}
+; CHECK-LABEL: test_vextq_s64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #8
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xS64x2 = alloca <2 x i64>, align 16
%__a = alloca <2 x i64>, align 16
%__b = alloca <2 x i64>, align 16
@@ -420,8 +566,15 @@ define void @test_vextq_s64() nounwind ssp {
}
define void @test_vextq_u64() nounwind ssp {
- ; CHECK-LABEL: test_vextq_u64:
- ; CHECK: {{ext.16.*#8}}
+; CHECK-LABEL: test_vextq_u64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ext.16b v1, v0, v0, #8
+; CHECK-NEXT: stp q0, q0, [sp]
+; CHECK-NEXT: str q1, [sp, #32]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: ret
%xU64x2 = alloca <2 x i64>, align 16
%__a = alloca <2 x i64>, align 16
%__b = alloca <2 x i64>, align 16
@@ -445,18 +598,21 @@ define void @test_vextq_u64() nounwind ssp {
; rdar://12051674
define <16 x i8> @vext1(<16 x i8> %_a) nounwind {
; CHECK-LABEL: vext1:
-; CHECK: ext.16b v0, v0, v0, #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-NEXT: ret
%vext = shufflevector <16 x i8> %_a, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <16 x i8> %vext
}
; <rdar://problem/12212062>
define <2 x i64> @vext2(<2 x i64> %p0, <2 x i64> %p1) nounwind readnone ssp {
-entry:
; CHECK-LABEL: vext2:
-; CHECK: add.2d v0, v0, v1
-; CHECK-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: add.2d v0, v0, v1
+; CHECK-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-NEXT: ret
+entry:
%t0 = shufflevector <2 x i64> %p1, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
%t1 = shufflevector <2 x i64> %p0, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
%t2 = add <2 x i64> %t1, %t0
diff --git a/llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll b/llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll
index c51ea17..9829ca3 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll
@@ -1,172 +1,217 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=arm64-linux-gnuabi < %s | FileCheck %s
-; The following tests is to check the correctness of reversing input operand
+; The following tests is to check the correctness of reversing input operand
; of vext by enumerating all cases of using two undefs in shuffle masks.
define <4 x i16> @vext_6701_0(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_0:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_12(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_12:
-; CHECK: dup v0.2s, v0.s[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.2s, v0.s[0]
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_13(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_13:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 undef, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_14(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_14:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 0, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_23(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_23:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 undef, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_24(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_24:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 0, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_34(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_6701_34:
-; CHECK: dup v0.2s, v1.s[1]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: dup v0.2s, v1.s[1]
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 undef, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_0(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_0:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_12(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_12:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 7, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_13(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_13:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 undef, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_14(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_14:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 7, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_23(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_23:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 undef, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_24(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_24:
-; CHECK: rev32 v0.4h, v1.4h
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev32 v0.4h, v1.4h
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 7, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_34(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_5670_34:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 undef, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_0(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_0:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_12(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_12:
-; CHECK: ext v0.8b, v0.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v0.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 1, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_13(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_13:
-; CHECK: rev32 v0.4h, v0.4h
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev32 v0.4h, v0.4h
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 undef, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_14(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_14:
-; CHECK: ext v0.8b, v0.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v0.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_23(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_23:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 undef, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_24(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_24:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 1, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_34(<4 x i16> %a1, <4 x i16> %a2) {
-entry:
; CHECK-LABEL: vext_7012_34:
-; CHECK: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK-NEXT: ret
+entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 undef, i32 undef>
ret <4 x i16> %x
}
diff --git a/llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll b/llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll
index 1f1bfe6..6df8d2b 100644
--- a/llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll
+++ b/llvm/test/CodeGen/AArch64/extend_inreg_of_concat_subvectors.ll
@@ -1,20 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=arm64-apple-ios -mattr=+sve -o - %s | FileCheck %s
-; RUN: llc -mtriple=aarch64_be-unknown-linux -mattr=+sve -o - %s | FileCheck --check-prefix=CHECK-BE %s
-; RUN: llc -mtriple=arm64-apple-ios -mattr=+global-isel -mattr=+sve -o - %s | FileCheck %s
-; RUN: llc -mtriple=aarch64_be-unknown-linux -mattr=+global-isel -mattr=+sve -o - %s | FileCheck --check-prefix=CHECK-BE %s
+; RUN: llc -mtriple=arm64-apple-ios -mattr=+sve -o - %s | FileCheck %s --check-prefix=CHECK-LE-SD
+; RUN: llc -mtriple=aarch64_be-unknown-linux -mattr=+sve -o - %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -mtriple=arm64-apple-ios -global-isel -mattr=+sve -o - %s | FileCheck %s --check-prefix=CHECK-LE-GI
define void @zext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
-; CHECK-LABEL: zext_of_concat:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: add.2s v0, v0, v1
-; CHECK-NEXT: ldr q1, [x2]
-; CHECK-NEXT: ushll.2d v0, v0, #0
-; CHECK-NEXT: add.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x2]
-; CHECK-NEXT: ret
+; CHECK-LE-SD-LABEL: zext_of_concat:
+; CHECK-LE-SD: ; %bb.0:
+; CHECK-LE-SD-NEXT: ldr d0, [x0]
+; CHECK-LE-SD-NEXT: ldr d1, [x1]
+; CHECK-LE-SD-NEXT: add.2s v0, v0, v1
+; CHECK-LE-SD-NEXT: ldr q1, [x2]
+; CHECK-LE-SD-NEXT: ushll.2d v0, v0, #0
+; CHECK-LE-SD-NEXT: add.4s v0, v0, v1
+; CHECK-LE-SD-NEXT: str q0, [x2]
+; CHECK-LE-SD-NEXT: ret
;
; CHECK-BE-LABEL: zext_of_concat:
; CHECK-BE: // %bb.0:
@@ -28,6 +27,23 @@ define void @zext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
; CHECK-BE-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: st1 { v0.4s }, [x2]
; CHECK-BE-NEXT: ret
+;
+; CHECK-LE-GI-LABEL: zext_of_concat:
+; CHECK-LE-GI: ; %bb.0:
+; CHECK-LE-GI-NEXT: ldr d0, [x0]
+; CHECK-LE-GI-NEXT: ldr d1, [x1]
+; CHECK-LE-GI-NEXT: movi.2d v3, #0000000000000000
+; CHECK-LE-GI-NEXT: Lloh0:
+; CHECK-LE-GI-NEXT: adrp x8, lCPI0_0@PAGE
+; CHECK-LE-GI-NEXT: add.2s v2, v0, v1
+; CHECK-LE-GI-NEXT: Lloh1:
+; CHECK-LE-GI-NEXT: ldr q0, [x8, lCPI0_0@PAGEOFF]
+; CHECK-LE-GI-NEXT: ldr q1, [x2]
+; CHECK-LE-GI-NEXT: tbl.16b v0, { v2, v3 }, v0
+; CHECK-LE-GI-NEXT: add.4s v0, v0, v1
+; CHECK-LE-GI-NEXT: str q0, [x2]
+; CHECK-LE-GI-NEXT: ret
+; CHECK-LE-GI-NEXT: .loh AdrpLdr Lloh0, Lloh1
%i0.a = load <2 x i32>, ptr %a
%i0.b = load <2 x i32>, ptr %b
%i0 = add <2 x i32> %i0.a, %i0.b
@@ -40,19 +56,19 @@ define void @zext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
}
define void @zext_of_concat_extrause(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e) nounwind {
-; CHECK-LABEL: zext_of_concat_extrause:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: ldr d0, [x1]
-; CHECK-NEXT: ldr d1, [x0]
-; CHECK-NEXT: add.2s v0, v1, v0
-; CHECK-NEXT: movi.2d v1, #0000000000000000
-; CHECK-NEXT: mov.d v0[1], v0[0]
-; CHECK-NEXT: zip1.4s v1, v0, v1
-; CHECK-NEXT: str q0, [x4]
-; CHECK-NEXT: ldr q0, [x2]
-; CHECK-NEXT: add.4s v0, v1, v0
-; CHECK-NEXT: str q0, [x2]
-; CHECK-NEXT: ret
+; CHECK-LE-SD-LABEL: zext_of_concat_extrause:
+; CHECK-LE-SD: ; %bb.0:
+; CHECK-LE-SD-NEXT: ldr d0, [x1]
+; CHECK-LE-SD-NEXT: ldr d1, [x0]
+; CHECK-LE-SD-NEXT: add.2s v0, v1, v0
+; CHECK-LE-SD-NEXT: movi.2d v1, #0000000000000000
+; CHECK-LE-SD-NEXT: mov.d v0[1], v0[0]
+; CHECK-LE-SD-NEXT: zip1.4s v1, v0, v1
+; CHECK-LE-SD-NEXT: str q0, [x4]
+; CHECK-LE-SD-NEXT: ldr q0, [x2]
+; CHECK-LE-SD-NEXT: add.4s v0, v1, v0
+; CHECK-LE-SD-NEXT: str q0, [x2]
+; CHECK-LE-SD-NEXT: ret
;
; CHECK-BE-LABEL: zext_of_concat_extrause:
; CHECK-BE: // %bb.0:
@@ -68,6 +84,25 @@ define void @zext_of_concat_extrause(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e) nou
; CHECK-BE-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: st1 { v0.4s }, [x2]
; CHECK-BE-NEXT: ret
+;
+; CHECK-LE-GI-LABEL: zext_of_concat_extrause:
+; CHECK-LE-GI: ; %bb.0:
+; CHECK-LE-GI-NEXT: ldr d0, [x0]
+; CHECK-LE-GI-NEXT: ldr d1, [x1]
+; CHECK-LE-GI-NEXT: movi.2d v3, #0000000000000000
+; CHECK-LE-GI-NEXT: Lloh2:
+; CHECK-LE-GI-NEXT: adrp x8, lCPI1_0@PAGE
+; CHECK-LE-GI-NEXT: add.2s v2, v0, v1
+; CHECK-LE-GI-NEXT: Lloh3:
+; CHECK-LE-GI-NEXT: ldr q0, [x8, lCPI1_0@PAGEOFF]
+; CHECK-LE-GI-NEXT: mov.d v2[1], v2[0]
+; CHECK-LE-GI-NEXT: tbl.16b v0, { v2, v3 }, v0
+; CHECK-LE-GI-NEXT: str q2, [x4]
+; CHECK-LE-GI-NEXT: ldr q1, [x2]
+; CHECK-LE-GI-NEXT: add.4s v0, v0, v1
+; CHECK-LE-GI-NEXT: str q0, [x2]
+; CHECK-LE-GI-NEXT: ret
+; CHECK-LE-GI-NEXT: .loh AdrpLdr Lloh2, Lloh3
%i0.a = load <2 x i32>, ptr %a
%i0.b = load <2 x i32>, ptr %b
%i0 = add <2 x i32> %i0.a, %i0.b
@@ -81,16 +116,16 @@ define void @zext_of_concat_extrause(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e) nou
}
define void @aext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
-; CHECK-LABEL: aext_of_concat:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: add.2s v0, v0, v1
-; CHECK-NEXT: ldr q1, [x2]
-; CHECK-NEXT: ushll.2d v0, v0, #0
-; CHECK-NEXT: add.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x2]
-; CHECK-NEXT: ret
+; CHECK-LE-SD-LABEL: aext_of_concat:
+; CHECK-LE-SD: ; %bb.0:
+; CHECK-LE-SD-NEXT: ldr d0, [x0]
+; CHECK-LE-SD-NEXT: ldr d1, [x1]
+; CHECK-LE-SD-NEXT: add.2s v0, v0, v1
+; CHECK-LE-SD-NEXT: ldr q1, [x2]
+; CHECK-LE-SD-NEXT: ushll.2d v0, v0, #0
+; CHECK-LE-SD-NEXT: add.4s v0, v0, v1
+; CHECK-LE-SD-NEXT: str q0, [x2]
+; CHECK-LE-SD-NEXT: ret
;
; CHECK-BE-LABEL: aext_of_concat:
; CHECK-BE: // %bb.0:
@@ -102,6 +137,17 @@ define void @aext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
; CHECK-BE-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: st1 { v0.4s }, [x2]
; CHECK-BE-NEXT: ret
+;
+; CHECK-LE-GI-LABEL: aext_of_concat:
+; CHECK-LE-GI: ; %bb.0:
+; CHECK-LE-GI-NEXT: ldr d0, [x0]
+; CHECK-LE-GI-NEXT: ldr d1, [x1]
+; CHECK-LE-GI-NEXT: add.2s v0, v0, v1
+; CHECK-LE-GI-NEXT: ldr q1, [x2]
+; CHECK-LE-GI-NEXT: zip1.4s v0, v0, v0
+; CHECK-LE-GI-NEXT: add.4s v0, v0, v1
+; CHECK-LE-GI-NEXT: str q0, [x2]
+; CHECK-LE-GI-NEXT: ret
%i0.a = load <2 x i32>, ptr %a
%i0.b = load <2 x i32>, ptr %b
%i0 = add <2 x i32> %i0.a, %i0.b
@@ -114,19 +160,19 @@ define void @aext_of_concat(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
}
define void @aext_of_concat_extrause(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e) nounwind {
-; CHECK-LABEL: aext_of_concat_extrause:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: ldr d0, [x1]
-; CHECK-NEXT: ldr d1, [x0]
-; CHECK-NEXT: add.2s v0, v1, v0
-; CHECK-NEXT: mov.16b v1, v0
-; CHECK-NEXT: mov.d v1[1], v0[0]
-; CHECK-NEXT: zip1.4s v0, v0, v0
-; CHECK-NEXT: str q1, [x4]
-; CHECK-NEXT: ldr q1, [x2]
-; CHECK-NEXT: add.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x2]
-; CHECK-NEXT: ret
+; CHECK-LE-SD-LABEL: aext_of_concat_extrause:
+; CHECK-LE-SD: ; %bb.0:
+; CHECK-LE-SD-NEXT: ldr d0, [x1]
+; CHECK-LE-SD-NEXT: ldr d1, [x0]
+; CHECK-LE-SD-NEXT: add.2s v0, v1, v0
+; CHECK-LE-SD-NEXT: mov.16b v1, v0
+; CHECK-LE-SD-NEXT: mov.d v1[1], v0[0]
+; CHECK-LE-SD-NEXT: zip1.4s v0, v0, v0
+; CHECK-LE-SD-NEXT: str q1, [x4]
+; CHECK-LE-SD-NEXT: ldr q1, [x2]
+; CHECK-LE-SD-NEXT: add.4s v0, v0, v1
+; CHECK-LE-SD-NEXT: str q0, [x2]
+; CHECK-LE-SD-NEXT: ret
;
; CHECK-BE-LABEL: aext_of_concat_extrause:
; CHECK-BE: // %bb.0:
@@ -141,6 +187,19 @@ define void @aext_of_concat_extrause(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e) nou
; CHECK-BE-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: st1 { v0.4s }, [x2]
; CHECK-BE-NEXT: ret
+;
+; CHECK-LE-GI-LABEL: aext_of_concat_extrause:
+; CHECK-LE-GI: ; %bb.0:
+; CHECK-LE-GI-NEXT: ldr d0, [x0]
+; CHECK-LE-GI-NEXT: ldr d1, [x1]
+; CHECK-LE-GI-NEXT: add.2s v0, v0, v1
+; CHECK-LE-GI-NEXT: mov.d v0[1], v0[0]
+; CHECK-LE-GI-NEXT: zip1.4s v1, v0, v0
+; CHECK-LE-GI-NEXT: str q0, [x4]
+; CHECK-LE-GI-NEXT: ldr q0, [x2]
+; CHECK-LE-GI-NEXT: add.4s v0, v1, v0
+; CHECK-LE-GI-NEXT: str q0, [x2]
+; CHECK-LE-GI-NEXT: ret
%i0.a = load <2 x i32>, ptr %a
%i0.b = load <2 x i32>, ptr %b
%i0 = add <2 x i32> %i0.a, %i0.b
diff --git a/llvm/test/CodeGen/AArch64/lifetime-poison.ll b/llvm/test/CodeGen/AArch64/lifetime-poison.ll
new file mode 100644
index 0000000..e04530d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/lifetime-poison.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64 -global-isel=0 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -global-isel=1 < %s | FileCheck %s
+
+; Check that lifetime.start/end with poison argument are ignored.
+
+define void @test() {
+; CHECK-LABEL: test:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ret
+ call void @llvm.lifetime.start.p0(i64 4, ptr poison)
+ call void @llvm.lifetime.end.p0(i64 4, ptr poison)
+ ret void
+}
diff --git a/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll b/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
new file mode 100644
index 0000000..988bb6f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
@@ -0,0 +1,900 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=RV32I
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+experimental-xqcilsm < %s \
+; RUN: | FileCheck %s -check-prefixes=RV32IXQCILSM
+
+%struct.anon = type { [16 x i32] }
+%struct.anon.0 = type { [47 x i32] }
+%struct.anon.1 = type { [48 x i32] }
+%struct.anon.2 = type { [64 x i8] }
+%struct.struct1_t = type { [16 x i32] }
+
+@struct1 = common dso_local local_unnamed_addr global %struct.anon zeroinitializer, align 4
+@struct4b = common dso_local local_unnamed_addr global %struct.anon.0 zeroinitializer, align 4
+@struct4b1 = common dso_local local_unnamed_addr global %struct.anon.1 zeroinitializer, align 4
+@struct2 = common dso_local local_unnamed_addr global %struct.anon.2 zeroinitializer, align 1
+@arr1 = common dso_local local_unnamed_addr global [100 x i32] zeroinitializer, align 4
+@struct1_ = common dso_local local_unnamed_addr global %struct.struct1_t zeroinitializer, align 4
+
+define void @test1(ptr nocapture %p, i32 %n) nounwind {
+; RV32I-LABEL: test1:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: mv a2, a1
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test1:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: mv a2, a1
+; RV32IXQCILSM-NEXT: li a1, 0
+; RV32IXQCILSM-NEXT: tail memset
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 1 %p, i8 0, i32 %n, i1 false)
+ ret void
+}
+
+declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1)
+
+define void @test2(ptr nocapture %p) nounwind {
+; RV32I-LABEL: test2:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 165
+; RV32I-NEXT: li a2, 128
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test2:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a1, 678490
+; RV32IXQCILSM-NEXT: addi a1, a1, 1445
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 64(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 %p, i8 -91, i32 128, i1 false)
+ ret void
+}
+
+define void @test2a(ptr nocapture %p) nounwind {
+; RV32I-LABEL: test2a:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 165
+; RV32I-NEXT: li a2, 188
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test2a:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a1, 678490
+; RV32IXQCILSM-NEXT: addi a1, a1, 1445
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 15, 64(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 124(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 %p, i8 -91, i32 188, i1 false)
+ ret void
+}
+
+define void @test2b(ptr nocapture %p) nounwind {
+; RV32I-LABEL: test2b:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 165
+; RV32I-NEXT: li a2, 192
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test2b:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: li a1, 165
+; RV32IXQCILSM-NEXT: li a2, 192
+; RV32IXQCILSM-NEXT: tail memset
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 %p, i8 -91, i32 192, i1 false)
+ ret void
+}
+
+define void @test2c(ptr nocapture %p) nounwind {
+; RV32I-LABEL: test2c:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 165
+; RV32I-NEXT: li a2, 128
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test2c:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a1, 678490
+; RV32IXQCILSM-NEXT: addi a1, a1, 1445
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 64(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 %p, i8 -91, i32 128, i1 false)
+ ret void
+}
+
+define void @test2d(ptr nocapture %p) nounwind {
+; RV32I-LABEL: test2d:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, -91
+; RV32I-NEXT: lui a2, 1048570
+; RV32I-NEXT: lui a3, 678490
+; RV32I-NEXT: addi a2, a2, 1445
+; RV32I-NEXT: addi a3, a3, 1445
+; RV32I-NEXT: sw a3, 0(a0)
+; RV32I-NEXT: sw a3, 4(a0)
+; RV32I-NEXT: sh a2, 8(a0)
+; RV32I-NEXT: sb a1, 10(a0)
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test2d:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: li a1, -91
+; RV32IXQCILSM-NEXT: lui a2, 1048570
+; RV32IXQCILSM-NEXT: lui a3, 678490
+; RV32IXQCILSM-NEXT: addi a2, a2, 1445
+; RV32IXQCILSM-NEXT: addi a3, a3, 1445
+; RV32IXQCILSM-NEXT: sw a3, 0(a0)
+; RV32IXQCILSM-NEXT: sw a3, 4(a0)
+; RV32IXQCILSM-NEXT: sh a2, 8(a0)
+; RV32IXQCILSM-NEXT: sb a1, 10(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 %p, i8 -91, i32 11, i1 false)
+ ret void
+}
+
+
+define ptr @test3(ptr %p) nounwind {
+; RV32I-LABEL: test3:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a2, 256
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test3:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: li a2, 256
+; RV32IXQCILSM-NEXT: li a1, 0
+; RV32IXQCILSM-NEXT: tail memset
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 %p, i8 0, i32 256, i1 false)
+ ret ptr %p
+}
+
+define ptr @test3a(ptr %p) nounwind {
+; RV32I-LABEL: test3a:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a2, 128
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test3a:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 64(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 %p, i8 0, i32 128, i1 false)
+ ret ptr %p
+}
+
+define void @test4() nounwind {
+; RV32I-LABEL: test4:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(struct1)
+; RV32I-NEXT: addi a0, a0, %lo(struct1)
+; RV32I-NEXT: li a2, 64
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test4:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(struct1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(struct1)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 0(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @struct1, i8 0, i32 64, i1 false)
+ ret void
+}
+
+define void @test4a(ptr nocapture %s) nounwind {
+; RV32I-LABEL: test4a:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a1, 166
+; RV32I-NEXT: li a2, 64
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test4a:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a1, 682602
+; RV32IXQCILSM-NEXT: addi a1, a1, 1702
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 0(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 %s, i8 -90, i32 64, i1 false)
+ ret void
+}
+
+declare void @llvm.lifetime.start.p0(i64, ptr nocapture)
+
+declare void @llvm.lifetime.end.p0(i64, ptr nocapture)
+
+define void @test4b() nounwind {
+; RV32I-LABEL: test4b:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a0, %hi(struct4b)
+; RV32I-NEXT: addi a0, a0, %lo(struct4b)
+; RV32I-NEXT: li a2, 188
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: call memset
+; RV32I-NEXT: lui a0, %hi(struct4b1)
+; RV32I-NEXT: addi a0, a0, %lo(struct4b1)
+; RV32I-NEXT: li a2, 192
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test4b:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a1, %hi(struct4b)
+; RV32IXQCILSM-NEXT: addi a1, a1, %lo(struct4b)
+; RV32IXQCILSM-NEXT: lui a0, %hi(struct4b1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(struct4b1)
+; RV32IXQCILSM-NEXT: li a2, 192
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 0(a1)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 15, 64(a1)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 124(a1)
+; RV32IXQCILSM-NEXT: li a1, 0
+; RV32IXQCILSM-NEXT: tail memset
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @struct4b, i8 0, i32 188, i1 false)
+ tail call void @llvm.memset.p0.i32(ptr align 4 @struct4b1, i8 0, i32 192, i1 false)
+ ret void
+}
+
+define void @test5() nounwind {
+; RV32I-LABEL: test5:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(struct2)
+; RV32I-NEXT: addi a0, a0, %lo(struct2)
+; RV32I-NEXT: li a2, 64
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test5:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(struct2)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(struct2)
+; RV32IXQCILSM-NEXT: li a2, 64
+; RV32IXQCILSM-NEXT: li a1, 0
+; RV32IXQCILSM-NEXT: tail memset
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 1 @struct2, i8 0, i32 64, i1 false)
+ ret void
+}
+
+define i32 @test6() nounwind {
+; RV32I-LABEL: test6:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw zero, 12(sp)
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test6:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: addi sp, sp, -16
+; RV32IXQCILSM-NEXT: sw zero, 12(sp)
+; RV32IXQCILSM-NEXT: li a0, 0
+; RV32IXQCILSM-NEXT: addi sp, sp, 16
+; RV32IXQCILSM-NEXT: ret
+entry:
+ %x = alloca i32, align 4
+ call void @llvm.memset.p0.i32(ptr align 4 %x, i8 0, i32 4, i1 false)
+ %0 = load i32, ptr %x, align 4
+ ret i32 %0
+}
+
+define zeroext i8 @test6b_c() nounwind {
+; RV32I-LABEL: test6b_c:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sb zero, 12(sp)
+; RV32I-NEXT: lbu a0, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test6b_c:
+; RV32IXQCILSM: # %bb.0:
+; RV32IXQCILSM-NEXT: addi sp, sp, -16
+; RV32IXQCILSM-NEXT: sb zero, 12(sp)
+; RV32IXQCILSM-NEXT: lbu a0, 12(sp)
+; RV32IXQCILSM-NEXT: addi sp, sp, 16
+; RV32IXQCILSM-NEXT: ret
+ %x = alloca i8, align 4
+ call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %x)
+ call void @llvm.memset.p0.i32(ptr nonnull align 4 %x, i8 0, i32 1, i1 false)
+ %x.0.x.0. = load volatile i8, ptr %x, align 4
+ call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %x)
+ ret i8 %x.0.x.0.
+}
+
+define signext i16 @test6b_s() nounwind {
+; RV32I-LABEL: test6b_s:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sh zero, 12(sp)
+; RV32I-NEXT: lh a0, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test6b_s:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: addi sp, sp, -16
+; RV32IXQCILSM-NEXT: sh zero, 12(sp)
+; RV32IXQCILSM-NEXT: lh a0, 12(sp)
+; RV32IXQCILSM-NEXT: addi sp, sp, 16
+; RV32IXQCILSM-NEXT: ret
+entry:
+ %x = alloca i16, align 4
+ call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %x)
+ store i16 0, ptr %x, align 4
+ %x.0.x.0. = load volatile i16, ptr %x, align 4
+ call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %x)
+ ret i16 %x.0.x.0.
+}
+
+define i32 @test6b_l() nounwind {
+; RV32I-LABEL: test6b_l:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw zero, 12(sp)
+; RV32I-NEXT: lw a0, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test6b_l:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: addi sp, sp, -16
+; RV32IXQCILSM-NEXT: sw zero, 12(sp)
+; RV32IXQCILSM-NEXT: lw a0, 12(sp)
+; RV32IXQCILSM-NEXT: addi sp, sp, 16
+; RV32IXQCILSM-NEXT: ret
+entry:
+ %x = alloca i32, align 4
+ call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %x)
+ store i32 0, ptr %x, align 4
+ %x.0.x.0. = load volatile i32, ptr %x, align 4
+ call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %x)
+ ret i32 %x.0.x.0.
+}
+
+define i64 @test6b_ll() nounwind {
+; RV32I-LABEL: test6b_ll:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw zero, 8(sp)
+; RV32I-NEXT: sw zero, 12(sp)
+; RV32I-NEXT: lw a0, 8(sp)
+; RV32I-NEXT: lw a1, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test6b_ll:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: addi sp, sp, -16
+; RV32IXQCILSM-NEXT: sw zero, 8(sp)
+; RV32IXQCILSM-NEXT: sw zero, 12(sp)
+; RV32IXQCILSM-NEXT: lw a0, 8(sp)
+; RV32IXQCILSM-NEXT: lw a1, 12(sp)
+; RV32IXQCILSM-NEXT: addi sp, sp, 16
+; RV32IXQCILSM-NEXT: ret
+entry:
+ %x = alloca i64, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %x)
+ call void @llvm.memset.p0.i32(ptr nonnull align 8 %x, i8 0, i32 8, i1 false)
+ %x.0.x.0. = load volatile i64, ptr %x, align 8
+ call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %x)
+ ret i64 %x.0.x.0.
+}
+
+define zeroext i8 @test6c_c() nounwind {
+; RV32I-LABEL: test6c_c:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sb zero, 15(sp)
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test6c_c:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: addi sp, sp, -16
+; RV32IXQCILSM-NEXT: sb zero, 15(sp)
+; RV32IXQCILSM-NEXT: li a0, 0
+; RV32IXQCILSM-NEXT: addi sp, sp, 16
+; RV32IXQCILSM-NEXT: ret
+entry:
+ %x = alloca i8
+ call void @llvm.memset.p0.i32(ptr align 1 %x, i8 0, i32 1, i1 false)
+ %0 = load i8, ptr %x, align 1
+ ret i8 %0
+}
+
+define signext i16 @test6c_s() nounwind {
+; RV32I-LABEL: test6c_s:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sh zero, 14(sp)
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test6c_s:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: addi sp, sp, -16
+; RV32IXQCILSM-NEXT: sh zero, 14(sp)
+; RV32IXQCILSM-NEXT: li a0, 0
+; RV32IXQCILSM-NEXT: addi sp, sp, 16
+; RV32IXQCILSM-NEXT: ret
+entry:
+ %x = alloca i16
+ call void @llvm.memset.p0.i32(ptr align 2 %x, i8 0, i32 2, i1 false)
+ %0 = load i16, ptr %x, align 2
+ ret i16 %0
+}
+
+define i32 @test6c_l() nounwind {
+; RV32I-LABEL: test6c_l:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw zero, 12(sp)
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test6c_l:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: addi sp, sp, -16
+; RV32IXQCILSM-NEXT: sw zero, 12(sp)
+; RV32IXQCILSM-NEXT: li a0, 0
+; RV32IXQCILSM-NEXT: addi sp, sp, 16
+; RV32IXQCILSM-NEXT: ret
+entry:
+ %x = alloca i32, align 4
+ call void @llvm.memset.p0.i32(ptr align 4 %x, i8 0, i32 4, i1 false)
+ %0 = load i32, ptr %x, align 4
+ ret i32 %0
+}
+
+define i64 @test6c_ll() nounwind {
+; RV32I-LABEL: test6c_ll:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw zero, 8(sp)
+; RV32I-NEXT: sw zero, 12(sp)
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test6c_ll:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: addi sp, sp, -16
+; RV32IXQCILSM-NEXT: sw zero, 8(sp)
+; RV32IXQCILSM-NEXT: sw zero, 12(sp)
+; RV32IXQCILSM-NEXT: li a0, 0
+; RV32IXQCILSM-NEXT: li a1, 0
+; RV32IXQCILSM-NEXT: addi sp, sp, 16
+; RV32IXQCILSM-NEXT: ret
+entry:
+ %x = alloca i64, align 8
+ call void @llvm.memset.p0.i32(ptr align 8 %x, i8 0, i32 8, i1 false)
+ %0 = load i64, ptr %x, align 8
+ ret i64 %0
+}
+
+define void @test7() nounwind {
+; RV32I-LABEL: test7:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: sw zero, %lo(arr1)(a0)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: sw zero, 4(a0)
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test7:
+; RV32IXQCILSM: # %bb.0:
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: sw zero, %lo(arr1)(a0)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: sw zero, 4(a0)
+; RV32IXQCILSM-NEXT: ret
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 8, i1 false)
+ ret void
+}
+
+define void @test7a() nounwind {
+; RV32I-LABEL: test7a:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test7a:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: ret
+entry:
+ call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 0, i1 false)
+ ret void
+}
+
+define void @test7a_unalign() nounwind {
+; RV32I-LABEL: test7a_unalign:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: li a1, -1
+; RV32I-NEXT: sw a1, %lo(arr1)(a0)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: sw a1, 8(a0)
+; RV32I-NEXT: sw a1, 12(a0)
+; RV32I-NEXT: sb a1, 16(a0)
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test7a_unalign:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: li a1, -1
+; RV32IXQCILSM-NEXT: sw a1, %lo(arr1)(a0)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: sw a1, 4(a0)
+; RV32IXQCILSM-NEXT: sw a1, 8(a0)
+; RV32IXQCILSM-NEXT: sw a1, 12(a0)
+; RV32IXQCILSM-NEXT: sb a1, 16(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 -1, i32 17, i1 false)
+ ret void
+}
+
+define void @test7b() nounwind {
+; RV32I-LABEL: test7b:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a1, 255
+; RV32I-NEXT: li a2, 68
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test7b:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: li a1, -1
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 1, 64(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 -1, i32 68, i1 false)
+ ret void
+}
+
+define void @test7c() nounwind {
+; RV32I-LABEL: test7c:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a1, 128
+; RV32I-NEXT: li a2, 128
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test7c:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: lui a1, 526344
+; RV32IXQCILSM-NEXT: addi a1, a1, 128
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 64(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 -128, i32 128, i1 false)
+ ret void
+}
+
+define void @test7d() nounwind {
+; RV32I-LABEL: test7d:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a1, 13
+; RV32I-NEXT: li a2, 148
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test7d:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: lui a1, 53457
+; RV32IXQCILSM-NEXT: addi a1, a1, -755
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 15, 64(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 6, 124(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 13, i32 148, i1 false)
+ ret void
+}
+
+define void @test7e() nounwind {
+; RV32I-LABEL: test7e:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a1, 239
+; RV32I-NEXT: li a2, 100
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test7e:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: lui a1, 982783
+; RV32IXQCILSM-NEXT: addi a1, a1, -17
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi a1, 9, 64(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 -17, i32 100, i1 false)
+ ret void
+}
+
+define void @test8() nounwind {
+; RV32I-LABEL: test8:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: sw zero, %lo(arr1)(a0)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: sw zero, 4(a0)
+; RV32I-NEXT: sw zero, 8(a0)
+; RV32I-NEXT: sw zero, 12(a0)
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test8:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: sw zero, %lo(arr1)(a0)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: sw zero, 4(a0)
+; RV32IXQCILSM-NEXT: sw zero, 8(a0)
+; RV32IXQCILSM-NEXT: sw zero, 12(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 16, i1 false)
+ ret void
+}
+
+define void @test9() nounwind {
+; RV32I-LABEL: test9:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: sw zero, %lo(arr1)(a0)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: sw zero, 20(a0)
+; RV32I-NEXT: sw zero, 24(a0)
+; RV32I-NEXT: sw zero, 28(a0)
+; RV32I-NEXT: sw zero, 4(a0)
+; RV32I-NEXT: sw zero, 8(a0)
+; RV32I-NEXT: sw zero, 12(a0)
+; RV32I-NEXT: sw zero, 16(a0)
+; RV32I-NEXT: ret
+;
+; RV32IXQCILSM-LABEL: test9:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: sw zero, %lo(arr1)(a0)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: sw zero, 20(a0)
+; RV32IXQCILSM-NEXT: sw zero, 24(a0)
+; RV32IXQCILSM-NEXT: sw zero, 28(a0)
+; RV32IXQCILSM-NEXT: sw zero, 4(a0)
+; RV32IXQCILSM-NEXT: sw zero, 8(a0)
+; RV32IXQCILSM-NEXT: sw zero, 12(a0)
+; RV32IXQCILSM-NEXT: sw zero, 16(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 32, i1 false)
+ ret void
+}
+
+define void @test10() nounwind {
+; RV32I-LABEL: test10:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a2, 60
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test10:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 15, 0(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 60, i1 false)
+ ret void
+}
+
+define void @test11() nounwind {
+; RV32I-LABEL: test11:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a2, 64
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test11:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 0(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 64, i1 false)
+ ret void
+}
+
+define void @test12() nounwind {
+; RV32I-LABEL: test12:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a2, 120
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test12:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 14, 64(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 120, i1 false)
+ ret void
+}
+
+define void @test13() nounwind {
+; RV32I-LABEL: test13:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a2, 124
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test13:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 15, 64(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 124, i1 false)
+ ret void
+}
+
+define void @test14() nounwind {
+; RV32I-LABEL: test14:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a2, 180
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test14:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 15, 64(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 14, 124(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 180, i1 false)
+ ret void
+}
+
+define void @test15() nounwind {
+; RV32I-LABEL: test15:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a2, 184
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test15:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 15, 64(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 15, 124(a0)
+; RV32IXQCILSM-NEXT: ret
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 184, i1 false)
+ ret void
+}
+
+define void @test15a() nounwind {
+; RV32I-LABEL: test15a:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a1, 165
+; RV32I-NEXT: li a2, 192
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test15a:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: li a1, 165
+; RV32IXQCILSM-NEXT: li a2, 192
+; RV32IXQCILSM-NEXT: tail memset
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 -91, i32 192, i1 false)
+ ret void
+}
+
+define void @test15b() nounwind {
+; RV32I-LABEL: test15b:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a2, 188
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test15b:
+; RV32IXQCILSM: # %bb.0:
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 0(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 15, 64(a0)
+; RV32IXQCILSM-NEXT: qc.setwmi zero, 16, 124(a0)
+; RV32IXQCILSM-NEXT: ret
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 188, i1 false)
+ ret void
+}
+
+define void @test15c() nounwind {
+; RV32I-LABEL: test15c:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lui a0, %hi(arr1)
+; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a2, 192
+; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: tail memset
+;
+; RV32IXQCILSM-LABEL: test15c:
+; RV32IXQCILSM: # %bb.0: # %entry
+; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
+; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: li a2, 192
+; RV32IXQCILSM-NEXT: li a1, 0
+; RV32IXQCILSM-NEXT: tail memset
+entry:
+ tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 192, i1 false)
+ ret void
+}
diff --git a/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll b/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll
index bbfe00b..9594370 100644
--- a/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll
@@ -334,6 +334,21 @@ entry:
ret void
}
+
+; Lifetimes on poison should be ignored.
+define void @lifetime_poison(i64 %a) #0 {
+; CHECK-LABEL: define void @lifetime_poison(
+; CHECK-SAME: i64 [[A:%.*]]) {
+; CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+; CHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
+; CHECK-NEXT: ret void
+;
+ %a.addr = alloca i64, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr poison)
+ store i64 %a, ptr %a.addr, align 8
+ call void @llvm.lifetime.end.p0(i64 8, ptr poison)
+ ret void
+}
;.
; CHECK-DEFAULT: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}
;.
diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/stack-safety-analysis.ll b/llvm/test/Instrumentation/HWAddressSanitizer/stack-safety-analysis.ll
index e96ca91..60af551 100644
--- a/llvm/test/Instrumentation/HWAddressSanitizer/stack-safety-analysis.ll
+++ b/llvm/test/Instrumentation/HWAddressSanitizer/stack-safety-analysis.ll
@@ -395,6 +395,25 @@ entry:
ret i32 0
}
+; Check that lifetimes on poison are ignored.
+define i32 @test_lifetime_poison(ptr %a) sanitize_hwaddress {
+entry:
+ ; CHECK-LABEL: @test_lifetime_poison
+ ; NOSAFETY: call {{.*}}__hwasan_generate_tag
+ ; NOSAFETY: call {{.*}}__hwasan_store
+ ; SAFETY-NOT: call {{.*}}__hwasan_generate_tag
+ ; SAFETY-NOT: call {{.*}}__hwasan_store
+ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag
+ ; NOSTACK-NOT: call {{.*}}__hwasan_store
+ ; SAFETY-REMARKS: --- !Passed{{[[:space:]]}}Pass: hwasan{{[[:space:]]}}Name: safeAlloca{{[[:space:]]}}Function: test_lifetime_poison
+ ; SAFETY-REMARKS: --- !Passed{{[[:space:]]}}Pass: hwasan{{[[:space:]]}}Name: ignoreAccess{{[[:space:]]}}Function: test_lifetime_poison
+ %buf.sroa.0 = alloca i8, align 4
+ call void @llvm.lifetime.start.p0(i64 1, ptr poison)
+ store volatile i8 0, ptr %buf.sroa.0, align 4, !tbaa !8
+ call void @llvm.lifetime.end.p0(i64 1, ptr poison)
+ ret i32 0
+}
+
; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
diff --git a/llvm/test/MC/ELF/many-instructions.s b/llvm/test/MC/ELF/many-instructions.s
deleted file mode 100644
index cbdb2a7..0000000
--- a/llvm/test/MC/ELF/many-instructions.s
+++ /dev/null
@@ -1,10 +0,0 @@
-# REQUIRES: asserts
-# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o /dev/null -debug-only=mc-dump
-
-## Test that encodeInstruction may cause a new fragment to be created.
-# CHECK: 0 Data Size:16200
-# CHECK: 16200 Data Size:180
-
-.rept 16384/10
-movabsq $foo, %rax
-.endr
diff --git a/llvm/test/MC/ELF/mc-dump.s b/llvm/test/MC/ELF/mc-dump.s
index 51b3ff4..a590e1c 100644
--- a/llvm/test/MC/ELF/mc-dump.s
+++ b/llvm/test/MC/ELF/mc-dump.s
@@ -30,7 +30,7 @@
# CHECK-NEXT:5 LEB Size:0+1 [15] Value:.Ltmp0-_start Signed:0
# CHECK:]
-# CHECK: 2 assembler - Number of fixup evaluations for relaxation
+# CHECK: 3 assembler - Number of fixup evaluations for relaxation
# CHECK: 8 assembler - Number of fixups
# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t -debug-only=mc-dump -save-temp-labels -g 2>&1 | FileCheck %s --check-prefix=CHECK2
diff --git a/llvm/test/Transforms/InstCombine/pr150338.ll b/llvm/test/Transforms/InstCombine/pr150338.ll
deleted file mode 100644
index 2ad454e..0000000
--- a/llvm/test/Transforms/InstCombine/pr150338.ll
+++ /dev/null
@@ -1,16 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -S -passes=instcombine < %s | FileCheck %s
-
-; Make sure this does not crash.
-define void @test(ptr %arg) {
-; CHECK-LABEL: define void @test(
-; CHECK-SAME: ptr [[ARG:%.*]]) {
-; CHECK-NEXT: store i1 true, ptr poison, align 1
-; CHECK-NEXT: ret void
-;
- %a = alloca i32
- store ptr %a, ptr %arg
- store i1 true, ptr poison
- call void @llvm.lifetime.end.p0(i64 4, ptr %a)
- ret void
-}
diff --git a/llvm/test/Transforms/InstCombine/unreachable-alloca-lifetime-markers.ll b/llvm/test/Transforms/InstCombine/unreachable-alloca-lifetime-markers.ll
new file mode 100644
index 0000000..ab744c62
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/unreachable-alloca-lifetime-markers.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S -passes=instcombine < %s | FileCheck %s
+
+; Make sure this does not crash.
+
+define void @pr150338(ptr %arg) {
+; CHECK-LABEL: define void @pr150338(
+; CHECK-SAME: ptr [[ARG:%.*]]) {
+; CHECK-NEXT: store i1 true, ptr poison, align 1
+; CHECK-NEXT: ret void
+;
+ %a = alloca i32
+ store ptr %a, ptr %arg
+ store i1 true, ptr poison
+ call void @llvm.lifetime.end.p0(i64 4, ptr %a)
+ ret void
+}
+
+define ptr @pr151119() {
+; CHECK-LABEL: define ptr @pr151119() {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: store i1 false, ptr poison, align 1
+; CHECK-NEXT: br i1 false, label %[[BB1:.*]], label %[[BB2:.*]]
+; CHECK: [[BB1]]:
+; CHECK-NEXT: br label %[[BB2]]
+; CHECK: [[BB2]]:
+; CHECK-NEXT: br label %[[BB1]]
+;
+entry:
+ %a = alloca i32, align 4
+ store i1 false, ptr poison
+ br i1 false, label %bb1, label %bb2
+
+bb1:
+ %phi1 = phi ptr [ null, %entry ], [ %phi2, %bb2 ]
+ call void @llvm.lifetime.start.p0(i64 4, ptr %a)
+ br label %bb2
+
+bb2:
+ %phi2 = phi ptr [ null, %entry ], [ %a, %bb1 ]
+ br label %bb1
+}
+
+define void @lifetime_poison() {
+; CHECK-LABEL: define void @lifetime_poison() {
+; CHECK-NEXT: ret void
+;
+ call void @llvm.lifetime.start.p0(i64 4, ptr poison)
+ call void @llvm.lifetime.end.p0(i64 4, ptr poison)
+ ret void
+}
diff --git a/llvm/test/tools/llvm-reduce/reduce-operands-alloca.ll b/llvm/test/tools/llvm-reduce/reduce-operands-alloca.ll
index 61c4618..b68f718 100644
--- a/llvm/test/tools/llvm-reduce/reduce-operands-alloca.ll
+++ b/llvm/test/tools/llvm-reduce/reduce-operands-alloca.ll
@@ -67,3 +67,15 @@ define void @alloca_constexpr_elt() {
store i32 0, ptr %alloca
ret void
}
+
+; CHECK-LABEL: @alloca_lifetimes(
+; ZERO: call void @llvm.lifetime.start.p0(i64 4, ptr %alloca)
+; ONE: call void @llvm.lifetime.start.p0(i64 4, ptr %alloca)
+; POISON: call void @llvm.lifetime.start.p0(i64 4, ptr %alloca)
+define void @alloca_lifetimes() {
+ %alloca = alloca i32
+ call void @llvm.lifetime.start.p0(i64 4, ptr %alloca)
+ store i32 0, ptr %alloca
+ call void @llvm.lifetime.end.p0(i64 4, ptr %alloca)
+ ret void
+}
generated by cgit v1.1 at 2025-08-04 13:18:41 +0000