diff options
Diffstat (limited to 'llvm/test/TableGen')
| -rw-r--r-- | llvm/test/TableGen/CompressInstEmitter/suboperands.td | 37 | ||||
| -rw-r--r-- | llvm/test/TableGen/RuntimeLibcallEmitter.td | 6 | ||||
| -rw-r--r-- | llvm/test/TableGen/SDNodeInfoEmitter/advanced.td (renamed from llvm/test/TableGen/SDNodeInfoEmitter/basic.td) | 97 | ||||
| -rw-r--r-- | llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints-1.td | 29 | ||||
| -rw-r--r-- | llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints-2.td (renamed from llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints.td) | 37 | ||||
| -rw-r--r-- | llvm/test/TableGen/SDNodeInfoEmitter/no-nodes.td | 50 | ||||
| -rw-r--r-- | llvm/test/TableGen/SDNodeInfoEmitter/trivial-node.td | 34 | ||||
| -rw-r--r-- | llvm/test/TableGen/get-named-operand-idx.td | 12 | ||||
| -rw-r--r-- | llvm/test/TableGen/getsetop.td | 14 | ||||
| -rw-r--r-- | llvm/test/TableGen/unsetop.td | 6 |
10 files changed, 162 insertions, 160 deletions
diff --git a/llvm/test/TableGen/CompressInstEmitter/suboperands.td b/llvm/test/TableGen/CompressInstEmitter/suboperands.td index d83cc04..f4e43d5 100644 --- a/llvm/test/TableGen/CompressInstEmitter/suboperands.td +++ b/llvm/test/TableGen/CompressInstEmitter/suboperands.td @@ -115,7 +115,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $addr // CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst); // CHECK-NEXT: // Operand: dst @@ -131,7 +131,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $src, $imm // CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst2); // CHECK-NEXT: // Operand: dst @@ -148,7 +148,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $addr // CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst3); // CHECK-NEXT: // Operand: dst @@ -161,16 +161,17 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: } // if // CHECK-LABEL: ArchValidateMCOperandForUncompress -// CHECK: // simm12 -// CHECK: return isInt<12>(Imm); +// CHECK: // simm6 +// CHECK: return isInt<6>(Imm); // CHECK-LABEL: uncompressInst // CHECK: case Arch::SmallInst: // CHECK-NEXT: if (MI.getOperand(0).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(0).getReg()) && +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1 /* simm6 */) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 2 /* simm12 */)) // CHECK-NEXT: // big $dst, $addr // CHECK-NEXT: OutInst.setOpcode(Arch::BigInst); // CHECK-NEXT: // Operand: dst @@ -183,10 +184,11 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: } // if // CHECK: case Arch::SmallInst2: // CHECK-NEXT: if (MI.getOperand(0).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(0).getReg()) && +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1 /* simm6 */) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 2 /* simm12 */)) { // CHECK-NEXT: // big $dst, $addr // CHECK-NEXT: OutInst.setOpcode(Arch::BigInst2); // CHECK-NEXT: // Operand: dst @@ -199,10 +201,11 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: } // if // CHECK: case Arch::SmallInst3: // CHECK-NEXT: if (MI.getOperand(0).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(0).getReg()) && +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1 /* simm6 */) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 2 /* simm12 */)) { // CHECK-NEXT: // big $dst, $src, $imm // CHECK-NEXT: OutInst.setOpcode(Arch::BigInst3); // CHECK-NEXT: // Operand: dst @@ -226,7 +229,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && // CHECK-NEXT: MI.getOperand(2).isImm() && -// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1)) { +// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $addr // CHECK-NEXT: // Operand: dst // CHECK-NEXT: // Operand: addr @@ -238,7 +241,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && // CHECK-NEXT: MI.getOperand(2).isImm() && -// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1)) { +// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $src, $imm // CHECK-NEXT: // Operand: dst // CHECK-NEXT: // Operand: src @@ -251,7 +254,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && // CHECK-NEXT: MI.getOperand(2).isImm() && -// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1)) { +// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $addr // CHECK-NEXT: // Operand: dst // CHECK-NEXT: // Operand: addr diff --git a/llvm/test/TableGen/RuntimeLibcallEmitter.td b/llvm/test/TableGen/RuntimeLibcallEmitter.td index 579e3c7..783a861 100644 --- a/llvm/test/TableGen/RuntimeLibcallEmitter.td +++ b/llvm/test/TableGen/RuntimeLibcallEmitter.td @@ -95,8 +95,8 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK-NEXT: __lshrdi3 = 4, // __lshrdi3 // CHECK-NEXT: bzero = 5, // bzero // CHECK-NEXT: calloc = 6, // calloc -// CHECK-NEXT: sqrtl_f80 = 7, // sqrtl -// CHECK-NEXT: sqrtl_f128 = 8, // sqrtl +// CHECK-NEXT: sqrtl_f128 = 7, // sqrtl +// CHECK-NEXT: sqrtl_f80 = 8, // sqrtl // CHECK-NEXT: NumLibcallImpls = 9 // CHECK-NEXT: }; // CHECK-NEXT: } // End namespace RTLIB @@ -157,8 +157,8 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK-NEXT: RTLIB::SRL_I64, // RTLIB::__lshrdi3 // CHECK-NEXT: RTLIB::BZERO, // RTLIB::bzero // CHECK-NEXT: RTLIB::CALLOC, // RTLIB::calloc -// CHECK-NEXT: RTLIB::SQRT_F80, // RTLIB::sqrtl_f80 // CHECK-NEXT: RTLIB::SQRT_F128, // RTLIB::sqrtl_f128 +// CHECK-NEXT: RTLIB::SQRT_F80, // RTLIB::sqrtl_f80 // CHECK-NEXT: }; diff --git a/llvm/test/TableGen/SDNodeInfoEmitter/basic.td b/llvm/test/TableGen/SDNodeInfoEmitter/advanced.td index 2b4c76a..d7eeaba 100644 --- a/llvm/test/TableGen/SDNodeInfoEmitter/basic.td +++ b/llvm/test/TableGen/SDNodeInfoEmitter/advanced.td @@ -1,99 +1,4 @@ -// RUN: split-file %s %t - -//--- no-nodes.td -// RUN: llvm-tblgen -gen-sd-node-info -I %p/../../../include %t/no-nodes.td \ -// RUN: | FileCheck %t/no-nodes.td - -include "llvm/Target/Target.td" - -def MyTarget : Target; - -// CHECK: #ifdef GET_SDNODE_ENUM -// CHECK-NEXT: #undef GET_SDNODE_ENUM -// CHECK-EMPTY: -// CHECK-NEXT: namespace llvm::MyTargetISD { -// CHECK-EMPTY: -// CHECK-NEXT: static constexpr unsigned GENERATED_OPCODE_END = ISD::BUILTIN_OP_END; -// CHECK-EMPTY: -// CHECK-NEXT: } // namespace llvm::MyTargetISD -// CHECK-EMPTY: -// CHECK-NEXT: #endif // GET_SDNODE_ENUM -// CHECK-EMPTY: -// CHECK-NEXT: #ifdef GET_SDNODE_DESC -// CHECK-NEXT: #undef GET_SDNODE_DESC -// CHECK-EMPTY: -// CHECK-NEXT: namespace llvm { -// CHECK-EMPTY: -// CHECK-NEXT: #ifdef __GNUC__ -// CHECK-NEXT: #pragma GCC diagnostic push -// CHECK-NEXT: #pragma GCC diagnostic ignored "-Woverlength-strings" -// CHECK-NEXT: #endif -// CHECK-NEXT: static constexpr char MyTargetSDNodeNamesStorage[] = -// CHECK-NEXT: "\0" -// CHECK-NEXT: ; -// CHECK-NEXT: #ifdef __GNUC__ -// CHECK-NEXT: #pragma GCC diagnostic pop -// CHECK-NEXT: #endif -// CHECK-EMPTY: -// CHECK-NEXT: static constexpr llvm::StringTable -// CHECK-NEXT: MyTargetSDNodeNames = MyTargetSDNodeNamesStorage; -// CHECK-EMPTY: -// CHECK-NEXT: static const SDTypeConstraint MyTargetSDTypeConstraints[] = { -// CHECK-NEXT: /* dummy */ {SDTCisVT, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE} -// CHECK-NEXT: }; -// CHECK-EMPTY: -// CHECK-NEXT: static const SDNodeDesc MyTargetSDNodeDescs[] = { -// CHECK-NEXT: }; -// CHECK-EMPTY: -// CHECK-NEXT: static const SDNodeInfo MyTargetGenSDNodeInfo( -// CHECK-NEXT: /*NumOpcodes=*/0, MyTargetSDNodeDescs, -// CHECK-NEXT: MyTargetSDNodeNames, MyTargetSDTypeConstraints); -// CHECK-EMPTY: -// CHECK-NEXT: } // namespace llvm -// CHECK-EMPTY: -// CHECK-NEXT: #endif // GET_SDNODE_DESC - - -//--- trivial-node.td -// RUN: llvm-tblgen -gen-sd-node-info -I %p/../../../include %t/trivial-node.td \ -// RUN: | FileCheck %t/trivial-node.td - -include "llvm/Target/Target.td" - -def MyTarget : Target; - -def my_noop : SDNode<"MyTargetISD::NOOP", SDTypeProfile<0, 0, []>>; - -// CHECK: namespace llvm::MyTargetISD { -// CHECK-EMPTY: -// CHECK-NEXT: enum GenNodeType : unsigned { -// CHECK-NEXT: NOOP = ISD::BUILTIN_OP_END, -// CHECK-NEXT: }; -// CHECK-EMPTY: -// CHECK-NEXT: static constexpr unsigned GENERATED_OPCODE_END = NOOP + 1; -// CHECK-EMPTY: -// CHECK-NEXT: } // namespace llvm::MyTargetISD - -// CHECK: static constexpr char MyTargetSDNodeNamesStorage[] = -// CHECK-NEXT: "\0" -// CHECK-NEXT: "MyTargetISD::NOOP\0" -// CHECK-NEXT: ; - -// CHECK: static const SDTypeConstraint MyTargetSDTypeConstraints[] = { -// CHECK-NEXT: /* dummy */ {SDTCisVT, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE} -// CHECK-NEXT: }; -// CHECK-EMPTY: -// CHECK-NEXT: static const SDNodeDesc MyTargetSDNodeDescs[] = { -// CHECK-NEXT: {0, 0, 0, 0, 0, 1, 0, 0}, // NOOP -// CHECK-NEXT: }; -// CHECK-EMPTY: -// CHECK-NEXT: static const SDNodeInfo MyTargetGenSDNodeInfo( -// CHECK-NEXT: /*NumOpcodes=*/1, MyTargetSDNodeDescs, -// CHECK-NEXT: MyTargetSDNodeNames, MyTargetSDTypeConstraints); - -//--- advanced.td -// RUN: llvm-tblgen -gen-sd-node-info -I %p/../../../include %t/advanced.td \ -// RUN: | FileCheck %t/advanced.td +// RUN: llvm-tblgen -gen-sd-node-info -I %p/../../../include %s | FileCheck %s include "llvm/Target/Target.td" diff --git a/llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints-1.td b/llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints-1.td new file mode 100644 index 0000000..8b86f93 --- /dev/null +++ b/llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints-1.td @@ -0,0 +1,29 @@ +// RUN: llvm-tblgen -gen-sd-node-info -I %p/../../../include %s | FileCheck %s + +include "llvm/Target/Target.td" + +def MyTarget : Target; + +def my_node_a : SDNode<"MyTargetISD::NODE", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>>; +def my_node_b : SDNode<"MyTargetISD::NODE", SDTypeProfile<1, 0, [SDTCisVT<0, f32>]>>; + +// CHECK: enum GenNodeType : unsigned { +// CHECK-NEXT: NODE = ISD::BUILTIN_OP_END, +// CHECK-NEXT: }; + +// CHECK: static constexpr char MyTargetSDNodeNamesStorage[] = +// CHECK-NEXT: "\0" +// CHECK-NEXT: "MyTargetISD::NODE\0" +// CHECK-NEXT: ; + +// CHECK: static const SDTypeConstraint MyTargetSDTypeConstraints[] = { +// CHECK-NEXT: /* dummy */ {SDTCisVT, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE} +// CHECK-NEXT: }; +// CHECK-EMPTY: +// CHECK-NEXT: static const SDNodeDesc MyTargetSDNodeDescs[] = { +// CHECK-NEXT: {1, 0, 0, 0, 0, 1, 0, 0}, // NODE +// CHECK-NEXT: }; +// CHECK-EMPTY: +// CHECK-NEXT: static const SDNodeInfo MyTargetGenSDNodeInfo( +// CHECK-NEXT: /*NumOpcodes=*/1, MyTargetSDNodeDescs, +// CHECK-NEXT: MyTargetSDNodeNames, MyTargetSDTypeConstraints); diff --git a/llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints.td b/llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints-2.td index c09e219..29429e9 100644 --- a/llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints.td +++ b/llvm/test/TableGen/SDNodeInfoEmitter/ambiguous-constraints-2.td @@ -1,39 +1,4 @@ -// RUN: split-file %s %t - -//--- test1.td -// RUN: llvm-tblgen -gen-sd-node-info -I %p/../../../include %t/test1.td | FileCheck %t/test1.td - -include "llvm/Target/Target.td" - -def MyTarget : Target; - -def my_node_a : SDNode<"MyTargetISD::NODE", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>>; -def my_node_b : SDNode<"MyTargetISD::NODE", SDTypeProfile<1, 0, [SDTCisVT<0, f32>]>>; - -// CHECK: enum GenNodeType : unsigned { -// CHECK-NEXT: NODE = ISD::BUILTIN_OP_END, -// CHECK-NEXT: }; - -// CHECK: static constexpr char MyTargetSDNodeNamesStorage[] = -// CHECK-NEXT: "\0" -// CHECK-NEXT: "MyTargetISD::NODE\0" -// CHECK-NEXT: ; - -// CHECK: static const SDTypeConstraint MyTargetSDTypeConstraints[] = { -// CHECK-NEXT: /* dummy */ {SDTCisVT, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE} -// CHECK-NEXT: }; -// CHECK-EMPTY: -// CHECK-NEXT: static const SDNodeDesc MyTargetSDNodeDescs[] = { -// CHECK-NEXT: {1, 0, 0, 0, 0, 1, 0, 0}, // NODE -// CHECK-NEXT: }; -// CHECK-EMPTY: -// CHECK-NEXT: static const SDNodeInfo MyTargetGenSDNodeInfo( -// CHECK-NEXT: /*NumOpcodes=*/1, MyTargetSDNodeDescs, -// CHECK-NEXT: MyTargetSDNodeNames, MyTargetSDTypeConstraints); - - -//--- test2.td -// RUN: llvm-tblgen -gen-sd-node-info -I %p/../../../include %t/test2.td | FileCheck %t/test2.td +// RUN: llvm-tblgen -gen-sd-node-info -I %p/../../../include %s | FileCheck %s include "llvm/Target/Target.td" diff --git a/llvm/test/TableGen/SDNodeInfoEmitter/no-nodes.td b/llvm/test/TableGen/SDNodeInfoEmitter/no-nodes.td new file mode 100644 index 0000000..0c5c63d --- /dev/null +++ b/llvm/test/TableGen/SDNodeInfoEmitter/no-nodes.td @@ -0,0 +1,50 @@ +// RUN: llvm-tblgen -gen-sd-node-info -I %p/../../../include %s | FileCheck %s + +include "llvm/Target/Target.td" + +def MyTarget : Target; + +// CHECK: #ifdef GET_SDNODE_ENUM +// CHECK-NEXT: #undef GET_SDNODE_ENUM +// CHECK-EMPTY: +// CHECK-NEXT: namespace llvm::MyTargetISD { +// CHECK-EMPTY: +// CHECK-NEXT: static constexpr unsigned GENERATED_OPCODE_END = ISD::BUILTIN_OP_END; +// CHECK-EMPTY: +// CHECK-NEXT: } // namespace llvm::MyTargetISD +// CHECK-EMPTY: +// CHECK-NEXT: #endif // GET_SDNODE_ENUM +// CHECK-EMPTY: +// CHECK-NEXT: #ifdef GET_SDNODE_DESC +// CHECK-NEXT: #undef GET_SDNODE_DESC +// CHECK-EMPTY: +// CHECK-NEXT: namespace llvm { +// CHECK-EMPTY: +// CHECK-NEXT: #ifdef __GNUC__ +// CHECK-NEXT: #pragma GCC diagnostic push +// CHECK-NEXT: #pragma GCC diagnostic ignored "-Woverlength-strings" +// CHECK-NEXT: #endif +// CHECK-NEXT: static constexpr char MyTargetSDNodeNamesStorage[] = +// CHECK-NEXT: "\0" +// CHECK-NEXT: ; +// CHECK-NEXT: #ifdef __GNUC__ +// CHECK-NEXT: #pragma GCC diagnostic pop +// CHECK-NEXT: #endif +// CHECK-EMPTY: +// CHECK-NEXT: static constexpr llvm::StringTable +// CHECK-NEXT: MyTargetSDNodeNames = MyTargetSDNodeNamesStorage; +// CHECK-EMPTY: +// CHECK-NEXT: static const SDTypeConstraint MyTargetSDTypeConstraints[] = { +// CHECK-NEXT: /* dummy */ {SDTCisVT, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE} +// CHECK-NEXT: }; +// CHECK-EMPTY: +// CHECK-NEXT: static const SDNodeDesc MyTargetSDNodeDescs[] = { +// CHECK-NEXT: }; +// CHECK-EMPTY: +// CHECK-NEXT: static const SDNodeInfo MyTargetGenSDNodeInfo( +// CHECK-NEXT: /*NumOpcodes=*/0, MyTargetSDNodeDescs, +// CHECK-NEXT: MyTargetSDNodeNames, MyTargetSDTypeConstraints); +// CHECK-EMPTY: +// CHECK-NEXT: } // namespace llvm +// CHECK-EMPTY: +// CHECK-NEXT: #endif // GET_SDNODE_DESC diff --git a/llvm/test/TableGen/SDNodeInfoEmitter/trivial-node.td b/llvm/test/TableGen/SDNodeInfoEmitter/trivial-node.td new file mode 100644 index 0000000..4bdc70a --- /dev/null +++ b/llvm/test/TableGen/SDNodeInfoEmitter/trivial-node.td @@ -0,0 +1,34 @@ +// RUN: llvm-tblgen -gen-sd-node-info -I %p/../../../include %s | FileCheck %s + +include "llvm/Target/Target.td" + +def MyTarget : Target; + +def my_noop : SDNode<"MyTargetISD::NOOP", SDTypeProfile<0, 0, []>>; + +// CHECK: namespace llvm::MyTargetISD { +// CHECK-EMPTY: +// CHECK-NEXT: enum GenNodeType : unsigned { +// CHECK-NEXT: NOOP = ISD::BUILTIN_OP_END, +// CHECK-NEXT: }; +// CHECK-EMPTY: +// CHECK-NEXT: static constexpr unsigned GENERATED_OPCODE_END = NOOP + 1; +// CHECK-EMPTY: +// CHECK-NEXT: } // namespace llvm::MyTargetISD + +// CHECK: static constexpr char MyTargetSDNodeNamesStorage[] = +// CHECK-NEXT: "\0" +// CHECK-NEXT: "MyTargetISD::NOOP\0" +// CHECK-NEXT: ; + +// CHECK: static const SDTypeConstraint MyTargetSDTypeConstraints[] = { +// CHECK-NEXT: /* dummy */ {SDTCisVT, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE} +// CHECK-NEXT: }; +// CHECK-EMPTY: +// CHECK-NEXT: static const SDNodeDesc MyTargetSDNodeDescs[] = { +// CHECK-NEXT: {0, 0, 0, 0, 0, 1, 0, 0}, // NOOP +// CHECK-NEXT: }; +// CHECK-EMPTY: +// CHECK-NEXT: static const SDNodeInfo MyTargetGenSDNodeInfo( +// CHECK-NEXT: /*NumOpcodes=*/1, MyTargetSDNodeDescs, +// CHECK-NEXT: MyTargetSDNodeNames, MyTargetSDTypeConstraints); diff --git a/llvm/test/TableGen/get-named-operand-idx.td b/llvm/test/TableGen/get-named-operand-idx.td index f5c5d93..ab23edd 100644 --- a/llvm/test/TableGen/get-named-operand-idx.td +++ b/llvm/test/TableGen/get-named-operand-idx.td @@ -72,14 +72,10 @@ def InstD : InstBase { // CHECK: {0, 1, 2, -1, -1, }, // CHECK: {-1, -1, -1, 0, 1, }, // CHECK: }; -// CHECK: switch(Opcode) { -// CHECK: case MyNamespace::InstA: -// CHECK: return OperandMap[0][static_cast<unsigned>(Name)]; -// CHECK: case MyNamespace::InstB: -// CHECK: case MyNamespace::InstC: -// CHECK: return OperandMap[1][static_cast<unsigned>(Name)]; -// CHECK: default: return -1; -// CHECK: } +// CHECK: static constexpr uint8_t InstructionIndex[] = { +// CHECK: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK: }; +// CHECK: return OperandMap[InstructionIndex[Opcode]][(unsigned)Name]; // CHECK: } // CHECK: } // end namespace llvm::MyNamespace // CHECK: #endif //GET_INSTRINFO_NAMED_OPS diff --git a/llvm/test/TableGen/getsetop.td b/llvm/test/TableGen/getsetop.td index aac644f..031606f 100644 --- a/llvm/test/TableGen/getsetop.td +++ b/llvm/test/TableGen/getsetop.td @@ -28,6 +28,7 @@ def bob : Super; def test { dag orig = (foo 1, 2:$a, $b); dag another = (qux "hello", $world); + dag named = (foo:$root 1, 2:$a, $b); // CHECK: dag replaceWithBar = (bar 1, 2:$a, ?:$b); dag replaceWithBar = !setop(orig, bar); @@ -41,6 +42,19 @@ def test { // CHECK: dag getopToSetop = (foo "hello", ?:$world); dag getopToSetop = !setdagop(another, !getdagop(orig)); + // CHECK: dag setOpName = (foo:$baz 1, 2:$a, ?:$b); + dag setOpName = !setdagopname(orig, "baz"); + + // CHECK: dag getopNameToSetOpName = (foo:$root 1, 2:$a, ?:$b); + dag getopNameToSetOpName = !setdagopname(orig, !getdagopname(named)); + + // CHECK: dag setOpNameExpl = (foo:$baz 1, 2:$a, ?:$b); + dag setOpNameExpl = !setdagopname((foo 1, 2:$a, $b), "baz"); + + // CHECK: dag getopNameToSetOpNameExpl = (foo:$root 1, 2:$a, ?:$b); + dag getopNameToSetOpNameExpl = + !setdagopname(orig, !getdagopname((foo:$root 1, 2:$a, $b))); + // CHECK: dag getopToBangDag = (foo 1:$a, 2:$b, 3:$c); dag getopToBangDag = !dag(!getdagop(orig), [1, 2, 3], ["a", "b", "c"]); diff --git a/llvm/test/TableGen/unsetop.td b/llvm/test/TableGen/unsetop.td index 7a4f98a..54ede19 100644 --- a/llvm/test/TableGen/unsetop.td +++ b/llvm/test/TableGen/unsetop.td @@ -16,6 +16,12 @@ def test { dag undefSecond = !con((op 1), (? 2)); // CHECK: dag undefBoth = (? 1, 2); dag undefBoth = !con((? 1), (? 2)); + // CHECK: dag namedLHS = (op:$lhs 1, 2); + dag namedLHS = !con((op:$lhs 1), (op 2)); + // CHECK: dag namedRHS = (op:$rhs 1, 2); + dag namedRHS = !con((op 1), (op:$rhs 2)); + // CHECK: dag namedBoth = (op:$lhs 1, 2); + dag namedBoth = !con((op:$lhs 1), (op:$rhs 2)); #ifdef ERROR // ERROR: Concatenated Dag operators do not match: '(op 1)' vs. '(otherop 2)' |