diff options
Diffstat (limited to 'llvm/test/TableGen/CompressInstEmitter/suboperands.td')
| -rw-r--r-- | llvm/test/TableGen/CompressInstEmitter/suboperands.td | 37 |
1 files changed, 20 insertions, 17 deletions
diff --git a/llvm/test/TableGen/CompressInstEmitter/suboperands.td b/llvm/test/TableGen/CompressInstEmitter/suboperands.td index d83cc04..f4e43d5 100644 --- a/llvm/test/TableGen/CompressInstEmitter/suboperands.td +++ b/llvm/test/TableGen/CompressInstEmitter/suboperands.td @@ -115,7 +115,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $addr // CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst); // CHECK-NEXT: // Operand: dst @@ -131,7 +131,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $src, $imm // CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst2); // CHECK-NEXT: // Operand: dst @@ -148,7 +148,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $addr // CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst3); // CHECK-NEXT: // Operand: dst @@ -161,16 +161,17 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: } // if // CHECK-LABEL: ArchValidateMCOperandForUncompress -// CHECK: // simm12 -// CHECK: return isInt<12>(Imm); +// CHECK: // simm6 +// CHECK: return isInt<6>(Imm); // CHECK-LABEL: uncompressInst // CHECK: case Arch::SmallInst: // CHECK-NEXT: if (MI.getOperand(0).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(0).getReg()) && +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1 /* simm6 */) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 2 /* simm12 */)) // CHECK-NEXT: // big $dst, $addr // CHECK-NEXT: OutInst.setOpcode(Arch::BigInst); // CHECK-NEXT: // Operand: dst @@ -183,10 +184,11 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: } // if // CHECK: case Arch::SmallInst2: // CHECK-NEXT: if (MI.getOperand(0).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(0).getReg()) && +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1 /* simm6 */) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 2 /* simm12 */)) { // CHECK-NEXT: // big $dst, $addr // CHECK-NEXT: OutInst.setOpcode(Arch::BigInst2); // CHECK-NEXT: // Operand: dst @@ -199,10 +201,11 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: } // if // CHECK: case Arch::SmallInst3: // CHECK-NEXT: if (MI.getOperand(0).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(0).getReg()) && +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) && // CHECK-NEXT: MI.getOperand(1).isReg() && -// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(1).getReg()) && -// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) { +// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1 /* simm6 */) && +// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 2 /* simm12 */)) { // CHECK-NEXT: // big $dst, $src, $imm // CHECK-NEXT: OutInst.setOpcode(Arch::BigInst3); // CHECK-NEXT: // Operand: dst @@ -226,7 +229,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && // CHECK-NEXT: MI.getOperand(2).isImm() && -// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1)) { +// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $addr // CHECK-NEXT: // Operand: dst // CHECK-NEXT: // Operand: addr @@ -238,7 +241,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && // CHECK-NEXT: MI.getOperand(2).isImm() && -// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1)) { +// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $src, $imm // CHECK-NEXT: // Operand: dst // CHECK-NEXT: // Operand: src @@ -251,7 +254,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm), // CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() && // CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) && // CHECK-NEXT: MI.getOperand(2).isImm() && -// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1)) { +// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1 /* simm6 */)) { // CHECK-NEXT: // small $dst, $addr // CHECK-NEXT: // Operand: dst // CHECK-NEXT: // Operand: addr |