diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV')
18 files changed, 842 insertions, 243 deletions
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll index 80a900f..3225120 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll @@ -1302,13 +1302,13 @@ define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; RV32I-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.agg.result) ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C4]](s32) + ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C4]](s32) ; RV32I-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.b) ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV32I-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C5]](s32) + ; RV32I-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C5]](s32) ; RV32I-NEXT: G_STORE [[C2]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %ir.c) ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 - ; RV32I-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C6]](s32) + ; RV32I-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C6]](s32) ; RV32I-NEXT: G_STORE [[C3]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %ir.d) ; RV32I-NEXT: PseudoRET store i32 1, ptr %agg.result, align 4 @@ -1331,7 +1331,7 @@ define i32 @caller_large_struct_ret() nounwind { ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s32) from %ir.1) ; ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 - ; ILP32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) + ; ILP32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; ILP32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s32) from %ir.3) ; ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]] ; ILP32-NEXT: $x10 = COPY [[ADD]](s32) @@ -1346,7 +1346,7 @@ define i32 @caller_large_struct_ret() nounwind { ; ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32F-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s32) from %ir.1) ; ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 - ; ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) + ; ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; ILP32F-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s32) from %ir.3) ; ILP32F-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]] ; ILP32F-NEXT: $x10 = COPY [[ADD]](s32) @@ -1361,7 +1361,7 @@ define i32 @caller_large_struct_ret() nounwind { ; ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s32) from %ir.1) ; ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 - ; ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) + ; ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; ILP32D-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s32) from %ir.3) ; ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]] ; ILP32D-NEXT: $x10 = COPY [[ADD]](s32) @@ -1392,13 +1392,13 @@ define %struct.large2 @callee_large_struct_ret2() nounwind { ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; RV32I-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32), align 8) ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C4]](s32) + ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s32) ; RV32I-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32)) ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV32I-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C5]](s32) + ; RV32I-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s32) ; RV32I-NEXT: G_STORE [[C2]](s16), [[PTR_ADD1]](p0) :: (store (s16), align 8) ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 - ; RV32I-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C6]](s32) + ; RV32I-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s32) ; RV32I-NEXT: G_STORE [[C3]](s32), [[PTR_ADD2]](p0) :: (store (s32)) ; RV32I-NEXT: PseudoRET %a = insertvalue %struct.large2 poison, i32 1, 0 @@ -1418,13 +1418,13 @@ define i32 @caller_large_struct_ret2() nounwind { ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %stack.0, align 8) ; ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; ILP32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) + ; ILP32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; ILP32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from %stack.0) ; ILP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; ILP32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C1]](s32) + ; ILP32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](s32) ; ILP32-NEXT: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p0) :: (load (s16) from %stack.0, align 8) ; ILP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 - ; ILP32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C2]](s32) + ; ILP32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](s32) ; ILP32-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %stack.0) ; ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD3]] ; ILP32-NEXT: $x10 = COPY [[ADD]](s32) @@ -1439,13 +1439,13 @@ define i32 @caller_large_struct_ret2() nounwind { ; ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32F-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %stack.0, align 8) ; ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) + ; ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; ILP32F-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from %stack.0) ; ILP32F-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; ILP32F-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C1]](s32) + ; ILP32F-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](s32) ; ILP32F-NEXT: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p0) :: (load (s16) from %stack.0, align 8) ; ILP32F-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 - ; ILP32F-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C2]](s32) + ; ILP32F-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](s32) ; ILP32F-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %stack.0) ; ILP32F-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD3]] ; ILP32F-NEXT: $x10 = COPY [[ADD]](s32) @@ -1460,13 +1460,13 @@ define i32 @caller_large_struct_ret2() nounwind { ; ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %stack.0, align 8) ; ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) + ; ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; ILP32D-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from %stack.0) ; ILP32D-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; ILP32D-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C1]](s32) + ; ILP32D-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](s32) ; ILP32D-NEXT: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p0) :: (load (s16) from %stack.0, align 8) ; ILP32D-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 - ; ILP32D-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C2]](s32) + ; ILP32D-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](s32) ; ILP32D-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %stack.0) ; ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD3]] ; ILP32D-NEXT: $x10 = COPY [[ADD]](s32) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll index af39faf..a297358 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll @@ -1075,13 +1075,13 @@ define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; RV64I-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.agg.result, align 4) ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 - ; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C4]](s64) + ; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C4]](s64) ; RV64I-NEXT: G_STORE [[C1]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.b, align 4) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 - ; RV64I-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C5]](s64) + ; RV64I-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C5]](s64) ; RV64I-NEXT: G_STORE [[C2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %ir.c, align 4) ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 - ; RV64I-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[COPY]], [[C6]](s64) + ; RV64I-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[COPY]], [[C6]](s64) ; RV64I-NEXT: G_STORE [[C3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %ir.d, align 4) ; RV64I-NEXT: PseudoRET store i64 1, ptr %agg.result, align 4 @@ -1104,7 +1104,7 @@ define i64 @caller_large_struct_ret() nounwind { ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.1) ; LP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 - ; LP64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) + ; LP64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; LP64-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s64) from %ir.3) ; LP64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD1]] ; LP64-NEXT: $x10 = COPY [[ADD]](s64) @@ -1119,7 +1119,7 @@ define i64 @caller_large_struct_ret() nounwind { ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.1) ; LP64F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 - ; LP64F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) + ; LP64F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; LP64F-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s64) from %ir.3) ; LP64F-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD1]] ; LP64F-NEXT: $x10 = COPY [[ADD]](s64) @@ -1134,7 +1134,7 @@ define i64 @caller_large_struct_ret() nounwind { ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.1) ; LP64D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 - ; LP64D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) + ; LP64D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; LP64D-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load (s64) from %ir.3) ; LP64D-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD1]] ; LP64D-NEXT: $x10 = COPY [[ADD]](s64) @@ -1165,13 +1165,13 @@ define %struct.large2 @callee_large_struct_ret2() nounwind { ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; RV64I-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64), align 16) ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 - ; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C4]](s64) + ; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64) ; RV64I-NEXT: G_STORE [[C1]](s128), [[PTR_ADD]](p0) :: (store (s128)) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 - ; RV64I-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C5]](s64) + ; RV64I-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C5]](s64) ; RV64I-NEXT: G_STORE [[C2]](s64), [[PTR_ADD1]](p0) :: (store (s64), align 16) ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 40 - ; RV64I-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C6]](s64) + ; RV64I-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C6]](s64) ; RV64I-NEXT: G_STORE [[C3]](s64), [[PTR_ADD2]](p0) :: (store (s64)) ; RV64I-NEXT: PseudoRET %a = insertvalue %struct.large2 poison, i64 1, 0 @@ -1191,13 +1191,13 @@ define i64 @caller_large_struct_ret2() nounwind { ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %stack.0, align 16) ; LP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 - ; LP64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) + ; LP64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; LP64-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %stack.0) ; LP64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 - ; LP64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C1]](s64) + ; LP64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](s64) ; LP64-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64) from %stack.0, align 16) ; LP64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 40 - ; LP64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C2]](s64) + ; LP64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](s64) ; LP64-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s64) from %stack.0) ; LP64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD3]] ; LP64-NEXT: $x10 = COPY [[ADD]](s64) @@ -1212,13 +1212,13 @@ define i64 @caller_large_struct_ret2() nounwind { ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64F-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %stack.0, align 16) ; LP64F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 - ; LP64F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) + ; LP64F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; LP64F-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %stack.0) ; LP64F-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 - ; LP64F-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C1]](s64) + ; LP64F-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](s64) ; LP64F-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64) from %stack.0, align 16) ; LP64F-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 40 - ; LP64F-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C2]](s64) + ; LP64F-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](s64) ; LP64F-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s64) from %stack.0) ; LP64F-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD3]] ; LP64F-NEXT: $x10 = COPY [[ADD]](s64) @@ -1233,13 +1233,13 @@ define i64 @caller_large_struct_ret2() nounwind { ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2 ; LP64D-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %stack.0, align 16) ; LP64D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 - ; LP64D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) + ; LP64D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; LP64D-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %stack.0) ; LP64D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 - ; LP64D-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C1]](s64) + ; LP64D-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C1]](s64) ; LP64D-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64) from %stack.0, align 16) ; LP64D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 40 - ; LP64D-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[FRAME_INDEX]], [[C2]](s64) + ; LP64D-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](s64) ; LP64D-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s64) from %stack.0) ; LP64D-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD3]] ; LP64D-NEXT: $x10 = COPY [[ADD]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll index 3b12ad5..e985d1f 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll @@ -67,7 +67,7 @@ define i32 @va1(ptr %fmt, ...) { ; RV32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va) ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (p0) from %ir.va) ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV32-NEXT: %20:_(p0) = nuw nusw G_PTR_ADD [[LOAD]], [[C1]](s32) + ; RV32-NEXT: %20:_(p0) = nuw nusw inbounds G_PTR_ADD [[LOAD]], [[C1]](s32) ; RV32-NEXT: G_STORE %20(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va) ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur) ; RV32-NEXT: $x10 = COPY [[LOAD1]](s32) @@ -105,7 +105,7 @@ define i32 @va1(ptr %fmt, ...) { ; RV64-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.va) ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (p0) from %ir.va, align 4) ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; RV64-NEXT: %20:_(p0) = nuw nusw G_PTR_ADD [[LOAD]], [[C1]](s64) + ; RV64-NEXT: %20:_(p0) = nuw nusw inbounds G_PTR_ADD [[LOAD]], [[C1]](s64) ; RV64-NEXT: G_STORE %20(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va, align 4) ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur) ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD1]](s32) @@ -687,7 +687,7 @@ define i64 @va2(ptr %fmt, ...) nounwind { ; RV32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]] ; RV32-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32) ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV32-NEXT: %25:_(p0) = nuw nusw G_PTR_ADD [[INTTOPTR]], [[C3]](s32) + ; RV32-NEXT: %25:_(p0) = nuw nusw inbounds G_PTR_ADD [[INTTOPTR]], [[C3]](s32) ; RV32-NEXT: G_STORE %25(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va) ; RV32-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32) ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3) @@ -733,7 +733,7 @@ define i64 @va2(ptr %fmt, ...) nounwind { ; RV64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]] ; RV64-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32) ; RV64-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 - ; RV64-NEXT: %25:_(p0) = nuw nusw G_PTR_ADD [[INTTOPTR]], [[C3]](s64) + ; RV64-NEXT: %25:_(p0) = nuw nusw inbounds G_PTR_ADD [[INTTOPTR]], [[C3]](s64) ; RV64-NEXT: G_STORE %25(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va, align 4) ; RV64-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32) ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3) @@ -974,7 +974,7 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind { ; RV32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]] ; RV32-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32) ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV32-NEXT: %24:_(p0) = nuw nusw G_PTR_ADD [[INTTOPTR]], [[C3]](s32) + ; RV32-NEXT: %24:_(p0) = nuw nusw inbounds G_PTR_ADD [[INTTOPTR]], [[C3]](s32) ; RV32-NEXT: G_STORE %24(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va) ; RV32-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32) ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3) @@ -1020,7 +1020,7 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind { ; RV64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]] ; RV64-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32) ; RV64-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 - ; RV64-NEXT: %25:_(p0) = nuw nusw G_PTR_ADD [[INTTOPTR]], [[C3]](s64) + ; RV64-NEXT: %25:_(p0) = nuw nusw inbounds G_PTR_ADD [[INTTOPTR]], [[C3]](s64) ; RV64-NEXT: G_STORE %25(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va, align 4) ; RV64-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32) ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3) @@ -1724,7 +1724,7 @@ define i32 @va_large_stack(ptr %fmt, ...) { ; RV32-NEXT: G_VASTART [[FRAME_INDEX2]](p0) :: (store (s32) into %ir.va) ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.va) ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV32-NEXT: %21:_(p0) = nuw nusw G_PTR_ADD [[LOAD]], [[C1]](s32) + ; RV32-NEXT: %21:_(p0) = nuw nusw inbounds G_PTR_ADD [[LOAD]], [[C1]](s32) ; RV32-NEXT: G_STORE %21(p0), [[FRAME_INDEX2]](p0) :: (store (p0) into %ir.va) ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur) ; RV32-NEXT: $x10 = COPY [[LOAD1]](s32) @@ -1763,7 +1763,7 @@ define i32 @va_large_stack(ptr %fmt, ...) { ; RV64-NEXT: G_VASTART [[FRAME_INDEX2]](p0) :: (store (s64) into %ir.va) ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.va, align 4) ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; RV64-NEXT: %21:_(p0) = nuw nusw G_PTR_ADD [[LOAD]], [[C1]](s64) + ; RV64-NEXT: %21:_(p0) = nuw nusw inbounds G_PTR_ADD [[LOAD]], [[C1]](s64) ; RV64-NEXT: G_STORE %21(p0), [[FRAME_INDEX2]](p0) :: (store (p0) into %ir.va, align 4) ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur) ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD1]](s32) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir index b2f98a8..e93f82a 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir @@ -1545,21 +1545,21 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 8) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C1]](s32) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s32) ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from unknown-address + 8, align 8) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s32) ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from unknown-address + 12) ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32), align 8) - ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s32) ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p0) :: (load (s32) from unknown-address + 4) - ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C1]](s32) + ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s32) ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p0) :: (load (s32) from unknown-address + 8, align 8) - ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C2]](s32) + ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s32) ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s32) from unknown-address + 12) ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[LOAD4]] ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD1]](s32), [[LOAD5]] diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir index bf7c341..9d2b6c1 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir @@ -147,7 +147,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 8) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4) ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32) ; CHECK-NEXT: $x11 = COPY [[LOAD1]](s32) @@ -159,7 +159,7 @@ body: | ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 8) ; UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s32) + ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) ; UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4) ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32) ; UNALIGNED-NEXT: $x11 = COPY [[LOAD1]](s32) @@ -232,7 +232,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16) @@ -278,15 +278,15 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD1]], [[C1]](s32) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s32) ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s32) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD2]] @@ -331,7 +331,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) @@ -376,15 +376,15 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD1]], [[C1]](s32) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s32) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s32) ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s32) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD2]] @@ -392,15 +392,15 @@ body: | ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32) ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]] ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C4]](s32) + ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s32) ; CHECK-NEXT: [[ZEXTLOAD3:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD3]](p0) :: (load (s8) from unknown-address + 4) - ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD3]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C]](s32) ; CHECK-NEXT: [[ZEXTLOAD4:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD4]](p0) :: (load (s8) from unknown-address + 5) ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD4]], [[C1]](s32) ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]] - ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD3]], [[C2]](s32) + ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C2]](s32) ; CHECK-NEXT: [[ZEXTLOAD5:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6) - ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD5]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD5]], [[C]](s32) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7) ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LOAD1]], [[C1]](s32) ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[SHL4]], [[ZEXTLOAD5]] @@ -416,7 +416,7 @@ body: | ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 1) ; UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s32) + ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32) ; UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4, align 1) ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32) ; UNALIGNED-NEXT: $x11 = COPY [[LOAD1]](s32) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir index 2424c4e..06e84fd 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir @@ -188,7 +188,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64)) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from unknown-address + 8) ; CHECK-NEXT: $x10 = COPY [[LOAD]](s64) ; CHECK-NEXT: $x11 = COPY [[LOAD1]](s64) @@ -200,7 +200,7 @@ body: | ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64)) ; UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 - ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64) + ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) ; UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from unknown-address + 8) ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s64) ; UNALIGNED-NEXT: $x11 = COPY [[LOAD1]](s64) @@ -273,7 +273,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16) @@ -320,15 +320,15 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD1]], [[C1]](s64) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64) ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s64) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C1]](s64) @@ -377,7 +377,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) @@ -423,15 +423,15 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD1]], [[C1]](s64) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64) ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD3:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD3]], [[C1]](s64) ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXTLOAD2]] @@ -439,15 +439,15 @@ body: | ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C3]](s64) ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[OR]] ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C4]](s64) + ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64) ; CHECK-NEXT: [[ZEXTLOAD4:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD3]](p0) :: (load (s8) from unknown-address + 4) - ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD3]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD5:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD4]](p0) :: (load (s8) from unknown-address + 5) ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD5]], [[C1]](s64) ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SHL3]], [[ZEXTLOAD4]] - ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD3]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C2]](s64) ; CHECK-NEXT: [[ZEXTLOAD6:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6) - ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD5]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD5]], [[C]](s64) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7) ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[LOAD]], [[C1]](s64) ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[ZEXTLOAD6]] @@ -494,15 +494,15 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD1]], [[C1]](s64) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64) ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s16) from unknown-address + 4) - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s64) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6) ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[LOAD]], [[C1]](s64) ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXTLOAD2]] @@ -549,15 +549,15 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD1]], [[C1]](s64) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64) ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD1]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD3:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD3]], [[C1]](s64) ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXTLOAD2]] @@ -565,15 +565,15 @@ body: | ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C3]](s64) ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[OR]] ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C4]](s64) + ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C4]](s64) ; CHECK-NEXT: [[ZEXTLOAD4:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD3]](p0) :: (load (s8) from unknown-address + 4) - ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD3]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD5:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD4]](p0) :: (load (s8) from unknown-address + 5) ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD5]], [[C1]](s64) ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SHL3]], [[ZEXTLOAD4]] - ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD3]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD3]], [[C2]](s64) ; CHECK-NEXT: [[ZEXTLOAD6:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6) - ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD5]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD5]], [[C]](s64) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7) ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[LOAD]], [[C1]](s64) ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[ZEXTLOAD6]] @@ -582,29 +582,29 @@ body: | ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[OR5]], [[C5]](s64) ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[OR2]] - ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C1]](s64) + ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64) ; CHECK-NEXT: [[ZEXTLOAD7:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD7]](p0) :: (load (s8) from unknown-address + 8) - ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD7]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD7]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD8:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD8]](p0) :: (load (s8) from unknown-address + 9) ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD8]], [[C1]](s64) ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s64) = G_OR [[SHL7]], [[ZEXTLOAD7]] - ; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD7]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD7]], [[C2]](s64) ; CHECK-NEXT: [[ZEXTLOAD9:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD9]](p0) :: (load (s8) from unknown-address + 10) - ; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD9]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD9]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD10:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD10]](p0) :: (load (s8) from unknown-address + 11) ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD10]], [[C1]](s64) ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s64) = G_OR [[SHL8]], [[ZEXTLOAD9]] ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[OR8]], [[C3]](s64) ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s64) = G_OR [[SHL9]], [[OR7]] - ; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD7]], [[C4]](s64) + ; CHECK-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD7]], [[C4]](s64) ; CHECK-NEXT: [[ZEXTLOAD11:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD11]](p0) :: (load (s8) from unknown-address + 12) - ; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD11]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD11]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD12:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD12]](p0) :: (load (s8) from unknown-address + 13) ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(s64) = G_SHL [[ZEXTLOAD12]], [[C1]](s64) ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s64) = G_OR [[SHL10]], [[ZEXTLOAD11]] - ; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD11]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD11]], [[C2]](s64) ; CHECK-NEXT: [[ZEXTLOAD13:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD13]](p0) :: (load (s8) from unknown-address + 14) - ; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD13]], [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD13]], [[C]](s64) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD14]](p0) :: (load (s8) from unknown-address + 15) ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(s64) = G_SHL [[LOAD1]], [[C1]](s64) ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s64) = G_OR [[SHL11]], [[ZEXTLOAD13]] @@ -622,7 +622,7 @@ body: | ; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64), align 1) ; UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 - ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C]](s64) + ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) ; UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from unknown-address + 8, align 1) ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s64) ; UNALIGNED-NEXT: $x11 = COPY [[LOAD1]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir index 9780abc..cb5db22 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir @@ -149,7 +149,7 @@ body: | ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 ; CHECK-NEXT: G_STORE [[COPY]](s32), [[COPY2]](p0) :: (store (s32), align 8) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY2]], [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY2]], [[C]](s32) ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 4) ; CHECK-NEXT: PseudoRET ; @@ -161,7 +161,7 @@ body: | ; UNALIGNED-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 ; UNALIGNED-NEXT: G_STORE [[COPY]](s32), [[COPY2]](p0) :: (store (s32), align 8) ; UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY2]], [[C]](s32) + ; UNALIGNED-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY2]], [[C]](s32) ; UNALIGNED-NEXT: G_STORE [[COPY1]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 4) ; UNALIGNED-NEXT: PseudoRET %2:_(s32) = COPY $x10 @@ -239,7 +239,7 @@ body: | ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C2]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s32) ; CHECK-NEXT: G_STORE [[COPY2]](s16), [[COPY1]](p0) :: (store (s8)) ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 1) ; CHECK-NEXT: PseudoRET @@ -284,7 +284,7 @@ body: | ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C1]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s32) ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 @@ -292,14 +292,14 @@ body: | ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s32) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C4]](s32) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s32) ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8)) ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1) ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[C5]](s32) ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32) - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD]], [[C4]](s32) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C4]](s32) ; CHECK-NEXT: G_STORE [[TRUNC2]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2) ; CHECK-NEXT: G_STORE [[TRUNC3]](s16), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3) ; CHECK-NEXT: PseudoRET @@ -342,7 +342,7 @@ body: | ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C1]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s32) ; CHECK-NEXT: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s16)) ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 2) ; CHECK-NEXT: PseudoRET diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir index c87a9e9..7c1ede0 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir @@ -268,7 +268,7 @@ body: | ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64) ; CHECK-NEXT: G_STORE [[COPY2]](s16), [[COPY1]](p0) :: (store (s8)) ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 1) ; CHECK-NEXT: PseudoRET @@ -315,7 +315,7 @@ body: | ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64) ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 @@ -323,7 +323,7 @@ body: | ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[C3]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s64) ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C5]](s64) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C5]](s64) ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s8)) ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1) ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64) @@ -331,7 +331,7 @@ body: | ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C4]] ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C6]](s64) ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s64) - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD]], [[C5]](s64) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C5]](s64) ; CHECK-NEXT: G_STORE [[TRUNC2]](s16), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2) ; CHECK-NEXT: G_STORE [[TRUNC3]](s16), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3) ; CHECK-NEXT: PseudoRET @@ -381,7 +381,7 @@ body: | ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C2]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C2]](s64) ; CHECK-NEXT: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s16)) ; CHECK-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 2) ; CHECK-NEXT: PseudoRET @@ -426,7 +426,7 @@ body: | ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY2]], [[C]](s64) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C1]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C1]](s64) ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 @@ -434,14 +434,14 @@ body: | ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C2]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64) ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY1]], [[C4]](s64) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C4]](s64) ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s16)) ; CHECK-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD1]](p0) :: (store (s16) into unknown-address + 2) ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64) ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[C5]](s64) ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR2]](s64) - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[PTR_ADD]], [[C4]](s64) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C4]](s64) ; CHECK-NEXT: G_STORE [[TRUNC2]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 4) ; CHECK-NEXT: G_STORE [[TRUNC3]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 6) ; CHECK-NEXT: PseudoRET diff --git a/llvm/test/CodeGen/RISCV/calleetypeid-directcall-mismatched.ll b/llvm/test/CodeGen/RISCV/calleetypeid-directcall-mismatched.ll new file mode 100644 index 0000000..34493ce --- /dev/null +++ b/llvm/test/CodeGen/RISCV/calleetypeid-directcall-mismatched.ll @@ -0,0 +1,33 @@ +;; Tests that callee_type metadata attached to direct call sites are safely ignored. + +; RUN: llc --call-graph-section -mtriple riscv64 < %s -stop-after=finalize-isel -o - | FileCheck --match-full-lines %s +; RUN: llc --call-graph-section -mtriple riscv32 < %s -stop-after=finalize-isel -o - | FileCheck --match-full-lines %s + +;; Test that `calleeTypeIds` field is not present in `callSites` +; CHECK-LABEL: callSites: +; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] } +; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] } +; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] } +define i32 @foo(i32 %x, i32 %y) !type !0 { +entry: + ;; Call instruction with accurate callee_type. + ;; callee_type should be dropped seemlessly. + %call = call i32 @fizz(i32 %x, i32 %y), !callee_type !1 + ;; Call instruction with mismatched callee_type. + ;; callee_type should be dropped seemlessly without errors. + %call1 = call i32 @fizz(i32 %x, i32 %y), !callee_type !3 + %add = add nsw i32 %call, %call1 + ;; Call instruction with mismatched callee_type. + ;; callee_type should be dropped seemlessly without errors. + %call2 = call i32 @fizz(i32 %add, i32 %y), !callee_type !3 + %sub = sub nsw i32 %add, %call2 + ret i32 %sub +} + +declare !type !2 i32 @fizz(i32, i32) + +!0 = !{i64 0, !"_ZTSFiiiiE.generalized"} +!1 = !{!2} +!2 = !{i64 0, !"_ZTSFiiiE.generalized"} +!3 = !{!4} +!4 = !{i64 0, !"_ZTSFicE.generalized"} diff --git a/llvm/test/CodeGen/RISCV/calling-conv-preserve-most.ll b/llvm/test/CodeGen/RISCV/calling-conv-preserve-most.ll new file mode 100644 index 0000000..08340bb --- /dev/null +++ b/llvm/test/CodeGen/RISCV/calling-conv-preserve-most.ll @@ -0,0 +1,449 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I +; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I +; RUN: llc -mtriple=riscv32 -mattr=+e -target-abi ilp32e < %s | FileCheck %s -check-prefix=RV32E +; RUN: llc -mtriple=riscv64 -mattr=+e -target-abi lp64e < %s | FileCheck %s -check-prefix=RV64E + +; Check the PreserveMost calling convention works. + +declare void @standard_cc_func() +declare preserve_mostcc void @preserve_mostcc_func() + +define preserve_mostcc void @preserve_mostcc1() nounwind { +; RV32I-LABEL: preserve_mostcc1: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT: addi sp, sp, -64 +; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t0, 56(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a1, 48(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a2, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a3, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a4, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a5, 32(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a6, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a7, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t4, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t5, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t6, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call standard_cc_func +; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t0, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a1, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a2, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a3, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a4, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a5, 32(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a6, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a7, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t4, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t5, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t6, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 64 +; RV32I-NEXT: ret +; +; RV64I-LABEL: preserve_mostcc1: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -112 +; RV64I-NEXT: sd ra, 104(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t0, 96(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a0, 88(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a1, 80(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a2, 72(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a3, 64(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a4, 56(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a5, 48(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a6, 40(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a7, 32(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t4, 24(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t5, 16(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t6, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: call standard_cc_func +; RV64I-NEXT: ld ra, 104(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t0, 96(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a0, 88(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a1, 80(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a2, 72(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a3, 64(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a4, 56(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a5, 48(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a6, 40(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a7, 32(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t4, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t5, 16(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t6, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 112 +; RV64I-NEXT: ret +; +; RV32E-LABEL: preserve_mostcc1: +; RV32E: # %bb.0: # %entry +; RV32E-NEXT: addi sp, sp, -32 +; RV32E-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32E-NEXT: sw t0, 24(sp) # 4-byte Folded Spill +; RV32E-NEXT: sw a0, 20(sp) # 4-byte Folded Spill +; RV32E-NEXT: sw a1, 16(sp) # 4-byte Folded Spill +; RV32E-NEXT: sw a2, 12(sp) # 4-byte Folded Spill +; RV32E-NEXT: sw a3, 8(sp) # 4-byte Folded Spill +; RV32E-NEXT: sw a4, 4(sp) # 4-byte Folded Spill +; RV32E-NEXT: sw a5, 0(sp) # 4-byte Folded Spill +; RV32E-NEXT: call standard_cc_func +; RV32E-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw t0, 24(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw a0, 20(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw a1, 16(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw a2, 12(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw a3, 8(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw a4, 4(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw a5, 0(sp) # 4-byte Folded Reload +; RV32E-NEXT: addi sp, sp, 32 +; RV32E-NEXT: ret +; +; RV64E-LABEL: preserve_mostcc1: +; RV64E: # %bb.0: # %entry +; RV64E-NEXT: addi sp, sp, -64 +; RV64E-NEXT: sd ra, 56(sp) # 8-byte Folded Spill +; RV64E-NEXT: sd t0, 48(sp) # 8-byte Folded Spill +; RV64E-NEXT: sd a0, 40(sp) # 8-byte Folded Spill +; RV64E-NEXT: sd a1, 32(sp) # 8-byte Folded Spill +; RV64E-NEXT: sd a2, 24(sp) # 8-byte Folded Spill +; RV64E-NEXT: sd a3, 16(sp) # 8-byte Folded Spill +; RV64E-NEXT: sd a4, 8(sp) # 8-byte Folded Spill +; RV64E-NEXT: sd a5, 0(sp) # 8-byte Folded Spill +; RV64E-NEXT: call standard_cc_func +; RV64E-NEXT: ld ra, 56(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld t0, 48(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld a0, 40(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld a1, 32(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld a2, 24(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld a3, 16(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld a4, 8(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld a5, 0(sp) # 8-byte Folded Reload +; RV64E-NEXT: addi sp, sp, 64 +; RV64E-NEXT: ret +entry: + call void @standard_cc_func() + ret void +} + +define preserve_mostcc void @preserve_mostcc2() nounwind { +; RV32I-LABEL: preserve_mostcc2: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call preserve_mostcc_func +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; +; RV64I-LABEL: preserve_mostcc2: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: call preserve_mostcc_func +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +; +; RV32E-LABEL: preserve_mostcc2: +; RV32E: # %bb.0: +; RV32E-NEXT: addi sp, sp, -4 +; RV32E-NEXT: sw ra, 0(sp) # 4-byte Folded Spill +; RV32E-NEXT: call preserve_mostcc_func +; RV32E-NEXT: lw ra, 0(sp) # 4-byte Folded Reload +; RV32E-NEXT: addi sp, sp, 4 +; RV32E-NEXT: ret +; +; RV64E-LABEL: preserve_mostcc2: +; RV64E: # %bb.0: +; RV64E-NEXT: addi sp, sp, -8 +; RV64E-NEXT: sd ra, 0(sp) # 8-byte Folded Spill +; RV64E-NEXT: call preserve_mostcc_func +; RV64E-NEXT: ld ra, 0(sp) # 8-byte Folded Reload +; RV64E-NEXT: addi sp, sp, 8 +; RV64E-NEXT: ret + call preserve_mostcc void @preserve_mostcc_func() + ret void +} + +; X6, X7 and X28 will be saved to registers. +define void @preserve_mostcc3() nounwind { +; RV32I-LABEL: preserve_mostcc3: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: mv a0, t1 +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: mv a1, t2 +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: mv a2, t3 +; RV32I-NEXT: call preserve_mostcc_func +; RV32I-NEXT: mv t1, a0 +; RV32I-NEXT: mv t2, a1 +; RV32I-NEXT: mv t3, a2 +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; +; RV64I-LABEL: preserve_mostcc3: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -32 +; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: mv a0, t1 +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: mv a1, t2 +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: mv a2, t3 +; RV64I-NEXT: call preserve_mostcc_func +; RV64I-NEXT: mv t1, a0 +; RV64I-NEXT: mv t2, a1 +; RV64I-NEXT: mv t3, a2 +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 32 +; RV64I-NEXT: ret +; +; RV32E-LABEL: preserve_mostcc3: +; RV32E: # %bb.0: +; RV32E-NEXT: addi sp, sp, -12 +; RV32E-NEXT: sw ra, 8(sp) # 4-byte Folded Spill +; RV32E-NEXT: sw s0, 4(sp) # 4-byte Folded Spill +; RV32E-NEXT: sw s1, 0(sp) # 4-byte Folded Spill +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: mv a0, t1 +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: mv a1, t2 +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: mv a2, t3 +; RV32E-NEXT: call preserve_mostcc_func +; RV32E-NEXT: mv t1, a0 +; RV32E-NEXT: mv t2, a1 +; RV32E-NEXT: mv t3, a2 +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: lw ra, 8(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw s0, 4(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw s1, 0(sp) # 4-byte Folded Reload +; RV32E-NEXT: addi sp, sp, 12 +; RV32E-NEXT: ret +; +; RV64E-LABEL: preserve_mostcc3: +; RV64E: # %bb.0: +; RV64E-NEXT: addi sp, sp, -24 +; RV64E-NEXT: sd ra, 16(sp) # 8-byte Folded Spill +; RV64E-NEXT: sd s0, 8(sp) # 8-byte Folded Spill +; RV64E-NEXT: sd s1, 0(sp) # 8-byte Folded Spill +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: mv a0, t1 +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: mv a1, t2 +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: mv a2, t3 +; RV64E-NEXT: call preserve_mostcc_func +; RV64E-NEXT: mv t1, a0 +; RV64E-NEXT: mv t2, a1 +; RV64E-NEXT: mv t3, a2 +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: ld ra, 16(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld s0, 8(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld s1, 0(sp) # 8-byte Folded Reload +; RV64E-NEXT: addi sp, sp, 24 +; RV64E-NEXT: ret + %1 = call i32 asm sideeffect "", "={x6}"() nounwind + %2 = call i32 asm sideeffect "", "={x7}"() nounwind + %3 = call i32 asm sideeffect "", "={x8}"() nounwind + %4 = call i32 asm sideeffect "", "={x9}"() nounwind + %5 = call i32 asm sideeffect "", "={x28}"() nounwind + call preserve_mostcc void @preserve_mostcc_func() + call void asm sideeffect "", "{x6},{x7},{x8},{x9},{x28}"(i32 %1, i32 %2, i32 %3, i32 %4, i32 %5) + ret void +} + +; X6, X7 and X28 will be saved to the stack. +define void @preserve_mostcc4() nounwind { +; RV32I-LABEL: preserve_mostcc4: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -32 +; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: mv s2, t1 +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: mv s3, t2 +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: mv s4, t3 +; RV32I-NEXT: call standard_cc_func +; RV32I-NEXT: mv t1, s2 +; RV32I-NEXT: mv t2, s3 +; RV32I-NEXT: mv t3, s4 +; RV32I-NEXT: #APP +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 32 +; RV32I-NEXT: ret +; +; RV64I-LABEL: preserve_mostcc4: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -48 +; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: mv s2, t1 +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: mv s3, t2 +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: mv s4, t3 +; RV64I-NEXT: call standard_cc_func +; RV64I-NEXT: mv t1, s2 +; RV64I-NEXT: mv t2, s3 +; RV64I-NEXT: mv t3, s4 +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 48 +; RV64I-NEXT: ret +; +; RV32E-LABEL: preserve_mostcc4: +; RV32E: # %bb.0: +; RV32E-NEXT: addi sp, sp, -24 +; RV32E-NEXT: sw ra, 20(sp) # 4-byte Folded Spill +; RV32E-NEXT: sw s0, 16(sp) # 4-byte Folded Spill +; RV32E-NEXT: sw s1, 12(sp) # 4-byte Folded Spill +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: sw t1, 8(sp) # 4-byte Folded Spill +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: sw t2, 4(sp) # 4-byte Folded Spill +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: sw t3, 0(sp) # 4-byte Folded Spill +; RV32E-NEXT: call standard_cc_func +; RV32E-NEXT: lw t1, 8(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw t2, 4(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw t3, 0(sp) # 4-byte Folded Reload +; RV32E-NEXT: #APP +; RV32E-NEXT: #NO_APP +; RV32E-NEXT: lw ra, 20(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw s0, 16(sp) # 4-byte Folded Reload +; RV32E-NEXT: lw s1, 12(sp) # 4-byte Folded Reload +; RV32E-NEXT: addi sp, sp, 24 +; RV32E-NEXT: ret +; +; RV64E-LABEL: preserve_mostcc4: +; RV64E: # %bb.0: +; RV64E-NEXT: addi sp, sp, -48 +; RV64E-NEXT: sd ra, 40(sp) # 8-byte Folded Spill +; RV64E-NEXT: sd s0, 32(sp) # 8-byte Folded Spill +; RV64E-NEXT: sd s1, 24(sp) # 8-byte Folded Spill +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: sd t1, 16(sp) # 8-byte Folded Spill +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: sd t2, 8(sp) # 8-byte Folded Spill +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: sd t3, 0(sp) # 8-byte Folded Spill +; RV64E-NEXT: call standard_cc_func +; RV64E-NEXT: ld t1, 16(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld t2, 8(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld t3, 0(sp) # 8-byte Folded Reload +; RV64E-NEXT: #APP +; RV64E-NEXT: #NO_APP +; RV64E-NEXT: ld ra, 40(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld s0, 32(sp) # 8-byte Folded Reload +; RV64E-NEXT: ld s1, 24(sp) # 8-byte Folded Reload +; RV64E-NEXT: addi sp, sp, 48 +; RV64E-NEXT: ret + %1 = call i32 asm sideeffect "", "={x6}"() nounwind + %2 = call i32 asm sideeffect "", "={x7}"() nounwind + %3 = call i32 asm sideeffect "", "={x8}"() nounwind + %4 = call i32 asm sideeffect "", "={x9}"() nounwind + %5 = call i32 asm sideeffect "", "={x28}"() nounwind + call void @standard_cc_func() + call void asm sideeffect "", "{x6},{x7},{x8},{x9},{x28}"(i32 %1, i32 %2, i32 %3, i32 %4, i32 %5) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/callsite-emit-calleetypeid-tailcall.ll b/llvm/test/CodeGen/RISCV/callsite-emit-calleetypeid-tailcall.ll new file mode 100644 index 0000000..6e1fe92 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/callsite-emit-calleetypeid-tailcall.ll @@ -0,0 +1,20 @@ +;; Tests that call site callee type ids can be extracted and set from +;; callee_type metadata for indirect tail calls. + +;; Verify the exact calleeTypeIds value to ensure it is not garbage but the value +;; computed as the type id from the callee_type operand bundle. +; RUN: llc --call-graph-section -mtriple riscv64 < %s -stop-after=finalize-isel -o - | FileCheck --match-full-lines %s +; RUN: llc --call-graph-section -mtriple riscv32 < %s -stop-after=finalize-isel -o - | FileCheck --match-full-lines %s + +define i32 @check_tailcall(ptr %func, i8 %x) !type !0 { +entry: + ; CHECK: callSites: + ; CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [], calleeTypeIds: + ; CHECK-NEXT: [ 3498816979441845844 ] } + %call = tail call i32 %func(i8 signext %x), !callee_type !1 + ret i32 %call +} + +!0 = !{i64 0, !"_ZTSFiPvcE.generalized"} +!1 = !{!2} +!2 = !{i64 0, !"_ZTSFicE.generalized"} diff --git a/llvm/test/CodeGen/RISCV/callsite-emit-calleetypeid.ll b/llvm/test/CodeGen/RISCV/callsite-emit-calleetypeid.ll new file mode 100644 index 0000000..1f91f41 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/callsite-emit-calleetypeid.ll @@ -0,0 +1,21 @@ +;; Tests that call site callee type ids can be extracted and set from +;; callee_type metadata. + +;; Verify the exact calleeTypeIds value to ensure it is not garbage but the value +;; computed as the type id from the callee_type operand bundle. +; RUN: llc --call-graph-section -mtriple riscv64 < %s -stop-after=finalize-isel -o - | FileCheck --match-full-lines %s +; RUN: llc --call-graph-section -mtriple riscv32 < %s -stop-after=finalize-isel -o - | FileCheck --match-full-lines %s + +; CHECK: name: main +; CHECK: callSites: +; CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [], calleeTypeIds: +; CHECK-NEXT: [ 7854600665770582568 ] } +define i32 @main() { +entry: + %fn = load ptr, ptr null, align 8 + call void %fn(i8 0), !callee_type !0 + ret i32 0 +} + +!0 = !{!1} +!1 = !{i64 0, !"_ZTSFvcE.generalized"} diff --git a/llvm/test/CodeGen/RISCV/memset-inline.ll b/llvm/test/CodeGen/RISCV/memset-inline.ll index 1263892..4091524 100644 --- a/llvm/test/CodeGen/RISCV/memset-inline.ll +++ b/llvm/test/CodeGen/RISCV/memset-inline.ll @@ -684,13 +684,13 @@ define void @aligned_memset_64(ptr align 64 %a, i8 %value) nounwind { ; ///////////////////////////////////////////////////////////////////////////// -define void @bzero_1(ptr %a) nounwind { -; RV32-BOTH-LABEL: bzero_1: +define void @memset_zero_1(ptr %a) nounwind { +; RV32-BOTH-LABEL: memset_zero_1: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sb zero, 0(a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: bzero_1: +; RV64-BOTH-LABEL: memset_zero_1: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sb zero, 0(a0) ; RV64-BOTH-NEXT: ret @@ -698,25 +698,25 @@ define void @bzero_1(ptr %a) nounwind { ret void } -define void @bzero_2(ptr %a) nounwind { -; RV32-LABEL: bzero_2: +define void @memset_zero_2(ptr %a) nounwind { +; RV32-LABEL: memset_zero_2: ; RV32: # %bb.0: ; RV32-NEXT: sb zero, 0(a0) ; RV32-NEXT: sb zero, 1(a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_2: +; RV64-LABEL: memset_zero_2: ; RV64: # %bb.0: ; RV64-NEXT: sb zero, 0(a0) ; RV64-NEXT: sb zero, 1(a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_2: +; RV32-FAST-LABEL: memset_zero_2: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: sh zero, 0(a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_2: +; RV64-FAST-LABEL: memset_zero_2: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: sh zero, 0(a0) ; RV64-FAST-NEXT: ret @@ -724,8 +724,8 @@ define void @bzero_2(ptr %a) nounwind { ret void } -define void @bzero_4(ptr %a) nounwind { -; RV32-LABEL: bzero_4: +define void @memset_zero_4(ptr %a) nounwind { +; RV32-LABEL: memset_zero_4: ; RV32: # %bb.0: ; RV32-NEXT: sb zero, 0(a0) ; RV32-NEXT: sb zero, 1(a0) @@ -733,7 +733,7 @@ define void @bzero_4(ptr %a) nounwind { ; RV32-NEXT: sb zero, 3(a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_4: +; RV64-LABEL: memset_zero_4: ; RV64: # %bb.0: ; RV64-NEXT: sb zero, 0(a0) ; RV64-NEXT: sb zero, 1(a0) @@ -741,12 +741,12 @@ define void @bzero_4(ptr %a) nounwind { ; RV64-NEXT: sb zero, 3(a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_4: +; RV32-FAST-LABEL: memset_zero_4: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: sw zero, 0(a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_4: +; RV64-FAST-LABEL: memset_zero_4: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: sw zero, 0(a0) ; RV64-FAST-NEXT: ret @@ -754,8 +754,8 @@ define void @bzero_4(ptr %a) nounwind { ret void } -define void @bzero_8(ptr %a) nounwind { -; RV32-LABEL: bzero_8: +define void @memset_zero_8(ptr %a) nounwind { +; RV32-LABEL: memset_zero_8: ; RV32: # %bb.0: ; RV32-NEXT: sb zero, 4(a0) ; RV32-NEXT: sb zero, 5(a0) @@ -767,7 +767,7 @@ define void @bzero_8(ptr %a) nounwind { ; RV32-NEXT: sb zero, 3(a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_8: +; RV64-LABEL: memset_zero_8: ; RV64: # %bb.0: ; RV64-NEXT: sb zero, 4(a0) ; RV64-NEXT: sb zero, 5(a0) @@ -779,13 +779,13 @@ define void @bzero_8(ptr %a) nounwind { ; RV64-NEXT: sb zero, 3(a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_8: +; RV32-FAST-LABEL: memset_zero_8: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: sw zero, 0(a0) ; RV32-FAST-NEXT: sw zero, 4(a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_8: +; RV64-FAST-LABEL: memset_zero_8: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: sd zero, 0(a0) ; RV64-FAST-NEXT: ret @@ -793,8 +793,8 @@ define void @bzero_8(ptr %a) nounwind { ret void } -define void @bzero_16(ptr %a) nounwind { -; RV32-LABEL: bzero_16: +define void @memset_zero_16(ptr %a) nounwind { +; RV32-LABEL: memset_zero_16: ; RV32: # %bb.0: ; RV32-NEXT: sb zero, 12(a0) ; RV32-NEXT: sb zero, 13(a0) @@ -814,7 +814,7 @@ define void @bzero_16(ptr %a) nounwind { ; RV32-NEXT: sb zero, 3(a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_16: +; RV64-LABEL: memset_zero_16: ; RV64: # %bb.0: ; RV64-NEXT: sb zero, 12(a0) ; RV64-NEXT: sb zero, 13(a0) @@ -834,7 +834,7 @@ define void @bzero_16(ptr %a) nounwind { ; RV64-NEXT: sb zero, 3(a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_16: +; RV32-FAST-LABEL: memset_zero_16: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: sw zero, 0(a0) ; RV32-FAST-NEXT: sw zero, 4(a0) @@ -842,7 +842,7 @@ define void @bzero_16(ptr %a) nounwind { ; RV32-FAST-NEXT: sw zero, 12(a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_16: +; RV64-FAST-LABEL: memset_zero_16: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: sd zero, 0(a0) ; RV64-FAST-NEXT: sd zero, 8(a0) @@ -851,8 +851,8 @@ define void @bzero_16(ptr %a) nounwind { ret void } -define void @bzero_32(ptr %a) nounwind { -; RV32-LABEL: bzero_32: +define void @memset_zero_32(ptr %a) nounwind { +; RV32-LABEL: memset_zero_32: ; RV32: # %bb.0: ; RV32-NEXT: sb zero, 28(a0) ; RV32-NEXT: sb zero, 29(a0) @@ -888,7 +888,7 @@ define void @bzero_32(ptr %a) nounwind { ; RV32-NEXT: sb zero, 3(a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_32: +; RV64-LABEL: memset_zero_32: ; RV64: # %bb.0: ; RV64-NEXT: sb zero, 28(a0) ; RV64-NEXT: sb zero, 29(a0) @@ -924,7 +924,7 @@ define void @bzero_32(ptr %a) nounwind { ; RV64-NEXT: sb zero, 3(a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_32: +; RV32-FAST-LABEL: memset_zero_32: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: sw zero, 16(a0) ; RV32-FAST-NEXT: sw zero, 20(a0) @@ -936,7 +936,7 @@ define void @bzero_32(ptr %a) nounwind { ; RV32-FAST-NEXT: sw zero, 12(a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_32: +; RV64-FAST-LABEL: memset_zero_32: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: sd zero, 0(a0) ; RV64-FAST-NEXT: sd zero, 8(a0) @@ -947,8 +947,8 @@ define void @bzero_32(ptr %a) nounwind { ret void } -define void @bzero_64(ptr %a) nounwind { -; RV32-LABEL: bzero_64: +define void @memset_zero_64(ptr %a) nounwind { +; RV32-LABEL: memset_zero_64: ; RV32: # %bb.0: ; RV32-NEXT: sb zero, 60(a0) ; RV32-NEXT: sb zero, 61(a0) @@ -1016,7 +1016,7 @@ define void @bzero_64(ptr %a) nounwind { ; RV32-NEXT: sb zero, 3(a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_64: +; RV64-LABEL: memset_zero_64: ; RV64: # %bb.0: ; RV64-NEXT: sb zero, 60(a0) ; RV64-NEXT: sb zero, 61(a0) @@ -1084,7 +1084,7 @@ define void @bzero_64(ptr %a) nounwind { ; RV64-NEXT: sb zero, 3(a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_64: +; RV32-FAST-LABEL: memset_zero_64: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: sw zero, 48(a0) ; RV32-FAST-NEXT: sw zero, 52(a0) @@ -1104,7 +1104,7 @@ define void @bzero_64(ptr %a) nounwind { ; RV32-FAST-NEXT: sw zero, 12(a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_64: +; RV64-FAST-LABEL: memset_zero_64: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: sd zero, 32(a0) ; RV64-FAST-NEXT: sd zero, 40(a0) @@ -1121,13 +1121,13 @@ define void @bzero_64(ptr %a) nounwind { ; ///////////////////////////////////////////////////////////////////////////// -define void @aligned_bzero_2(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_2: +define void @aligned_memset_zero_2(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_2: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sh zero, 0(a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_2: +; RV64-BOTH-LABEL: aligned_memset_zero_2: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sh zero, 0(a0) ; RV64-BOTH-NEXT: ret @@ -1135,13 +1135,13 @@ define void @aligned_bzero_2(ptr %a) nounwind { ret void } -define void @aligned_bzero_4(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_4: +define void @aligned_memset_zero_4(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_4: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sw zero, 0(a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_4: +; RV64-BOTH-LABEL: aligned_memset_zero_4: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sw zero, 0(a0) ; RV64-BOTH-NEXT: ret @@ -1149,14 +1149,14 @@ define void @aligned_bzero_4(ptr %a) nounwind { ret void } -define void @aligned_bzero_8(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_8: +define void @aligned_memset_zero_8(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_8: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sw zero, 0(a0) ; RV32-BOTH-NEXT: sw zero, 4(a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_8: +; RV64-BOTH-LABEL: aligned_memset_zero_8: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sd zero, 0(a0) ; RV64-BOTH-NEXT: ret @@ -1165,8 +1165,8 @@ define void @aligned_bzero_8(ptr %a) nounwind { } -define void @aligned_bzero_16(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_16: +define void @aligned_memset_zero_16(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_16: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sw zero, 0(a0) ; RV32-BOTH-NEXT: sw zero, 4(a0) @@ -1174,7 +1174,7 @@ define void @aligned_bzero_16(ptr %a) nounwind { ; RV32-BOTH-NEXT: sw zero, 12(a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_16: +; RV64-BOTH-LABEL: aligned_memset_zero_16: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sd zero, 0(a0) ; RV64-BOTH-NEXT: sd zero, 8(a0) @@ -1183,8 +1183,8 @@ define void @aligned_bzero_16(ptr %a) nounwind { ret void } -define void @aligned_bzero_32(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_32: +define void @aligned_memset_zero_32(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_32: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sw zero, 16(a0) ; RV32-BOTH-NEXT: sw zero, 20(a0) @@ -1196,7 +1196,7 @@ define void @aligned_bzero_32(ptr %a) nounwind { ; RV32-BOTH-NEXT: sw zero, 12(a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_32: +; RV64-BOTH-LABEL: aligned_memset_zero_32: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sd zero, 0(a0) ; RV64-BOTH-NEXT: sd zero, 8(a0) @@ -1207,8 +1207,8 @@ define void @aligned_bzero_32(ptr %a) nounwind { ret void } -define void @aligned_bzero_64(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_64: +define void @aligned_memset_zero_64(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_64: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sw zero, 48(a0) ; RV32-BOTH-NEXT: sw zero, 52(a0) @@ -1228,7 +1228,7 @@ define void @aligned_bzero_64(ptr %a) nounwind { ; RV32-BOTH-NEXT: sw zero, 12(a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_64: +; RV64-BOTH-LABEL: aligned_memset_zero_64: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sd zero, 32(a0) ; RV64-BOTH-NEXT: sd zero, 40(a0) @@ -1247,28 +1247,28 @@ define void @aligned_bzero_64(ptr %a) nounwind { ; ///////////////////////////////////////////////////////////////////////////// ; Usual overlap tricks -define void @aligned_bzero_7(ptr %a) nounwind { -; RV32-LABEL: aligned_bzero_7: +define void @aligned_memset_zero_7(ptr %a) nounwind { +; RV32-LABEL: aligned_memset_zero_7: ; RV32: # %bb.0: ; RV32-NEXT: sw zero, 0(a0) ; RV32-NEXT: sh zero, 4(a0) ; RV32-NEXT: sb zero, 6(a0) ; RV32-NEXT: ret ; -; RV64-LABEL: aligned_bzero_7: +; RV64-LABEL: aligned_memset_zero_7: ; RV64: # %bb.0: ; RV64-NEXT: sw zero, 0(a0) ; RV64-NEXT: sh zero, 4(a0) ; RV64-NEXT: sb zero, 6(a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: aligned_bzero_7: +; RV32-FAST-LABEL: aligned_memset_zero_7: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: sw zero, 3(a0) ; RV32-FAST-NEXT: sw zero, 0(a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: aligned_bzero_7: +; RV64-FAST-LABEL: aligned_memset_zero_7: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: sw zero, 3(a0) ; RV64-FAST-NEXT: sw zero, 0(a0) @@ -1277,8 +1277,8 @@ define void @aligned_bzero_7(ptr %a) nounwind { ret void } -define void @aligned_bzero_15(ptr %a) nounwind { -; RV32-LABEL: aligned_bzero_15: +define void @aligned_memset_zero_15(ptr %a) nounwind { +; RV32-LABEL: aligned_memset_zero_15: ; RV32: # %bb.0: ; RV32-NEXT: sb zero, 14(a0) ; RV32-NEXT: sw zero, 0(a0) @@ -1287,7 +1287,7 @@ define void @aligned_bzero_15(ptr %a) nounwind { ; RV32-NEXT: sh zero, 12(a0) ; RV32-NEXT: ret ; -; RV64-LABEL: aligned_bzero_15: +; RV64-LABEL: aligned_memset_zero_15: ; RV64: # %bb.0: ; RV64-NEXT: sd zero, 0(a0) ; RV64-NEXT: sw zero, 8(a0) @@ -1295,7 +1295,7 @@ define void @aligned_bzero_15(ptr %a) nounwind { ; RV64-NEXT: sb zero, 14(a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: aligned_bzero_15: +; RV32-FAST-LABEL: aligned_memset_zero_15: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: sw zero, 11(a0) ; RV32-FAST-NEXT: sw zero, 0(a0) @@ -1303,7 +1303,7 @@ define void @aligned_bzero_15(ptr %a) nounwind { ; RV32-FAST-NEXT: sw zero, 8(a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: aligned_bzero_15: +; RV64-FAST-LABEL: aligned_memset_zero_15: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: sd zero, 7(a0) ; RV64-FAST-NEXT: sd zero, 0(a0) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll index 5747bbb..bd37443 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll @@ -554,9 +554,8 @@ define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, ptr %svp) { ; VLA-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; VLA-NEXT: vmv.v.i v10, 0 ; VLA-NEXT: vmv1r.v v0, v8 -; VLA-NEXT: vmerge.vim v8, v10, 1, v0 ; VLA-NEXT: vsetvli zero, zero, e8, mf4, tu, ma -; VLA-NEXT: vmv.v.v v9, v8 +; VLA-NEXT: vmerge.vim v9, v10, 1, v0 ; VLA-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; VLA-NEXT: vmsne.vi v0, v9, 0 ; VLA-NEXT: ret @@ -568,9 +567,8 @@ define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, ptr %svp) { ; VLS-NEXT: vmv.v.i v9, 0 ; VLS-NEXT: vmerge.vim v10, v9, 1, v0 ; VLS-NEXT: vmv1r.v v0, v8 -; VLS-NEXT: vmerge.vim v8, v9, 1, v0 ; VLS-NEXT: vsetvli zero, zero, e8, mf4, tu, ma -; VLS-NEXT: vmv.v.v v10, v8 +; VLS-NEXT: vmerge.vim v10, v9, 1, v0 ; VLS-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; VLS-NEXT: vmsne.vi v0, v10, 0 ; VLS-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/memset-inline.ll b/llvm/test/CodeGen/RISCV/rvv/memset-inline.ll index 8963940..2c11bd1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/memset-inline.ll +++ b/llvm/test/CodeGen/RISCV/rvv/memset-inline.ll @@ -360,13 +360,13 @@ define void @aligned_memset_64(ptr align 64 %a, i8 %value) nounwind { ; ///////////////////////////////////////////////////////////////////////////// -define void @bzero_1(ptr %a) nounwind { -; RV32-BOTH-LABEL: bzero_1: +define void @memset_zero_1(ptr %a) nounwind { +; RV32-BOTH-LABEL: memset_zero_1: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sb zero, 0(a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: bzero_1: +; RV64-BOTH-LABEL: memset_zero_1: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sb zero, 0(a0) ; RV64-BOTH-NEXT: ret @@ -374,25 +374,25 @@ define void @bzero_1(ptr %a) nounwind { ret void } -define void @bzero_2(ptr %a) nounwind { -; RV32-LABEL: bzero_2: +define void @memset_zero_2(ptr %a) nounwind { +; RV32-LABEL: memset_zero_2: ; RV32: # %bb.0: ; RV32-NEXT: sb zero, 0(a0) ; RV32-NEXT: sb zero, 1(a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_2: +; RV64-LABEL: memset_zero_2: ; RV64: # %bb.0: ; RV64-NEXT: sb zero, 0(a0) ; RV64-NEXT: sb zero, 1(a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_2: +; RV32-FAST-LABEL: memset_zero_2: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: sh zero, 0(a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_2: +; RV64-FAST-LABEL: memset_zero_2: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: sh zero, 0(a0) ; RV64-FAST-NEXT: ret @@ -400,8 +400,8 @@ define void @bzero_2(ptr %a) nounwind { ret void } -define void @bzero_4(ptr %a) nounwind { -; RV32-LABEL: bzero_4: +define void @memset_zero_4(ptr %a) nounwind { +; RV32-LABEL: memset_zero_4: ; RV32: # %bb.0: ; RV32-NEXT: sb zero, 0(a0) ; RV32-NEXT: sb zero, 1(a0) @@ -409,7 +409,7 @@ define void @bzero_4(ptr %a) nounwind { ; RV32-NEXT: sb zero, 3(a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_4: +; RV64-LABEL: memset_zero_4: ; RV64: # %bb.0: ; RV64-NEXT: sb zero, 0(a0) ; RV64-NEXT: sb zero, 1(a0) @@ -417,12 +417,12 @@ define void @bzero_4(ptr %a) nounwind { ; RV64-NEXT: sb zero, 3(a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_4: +; RV32-FAST-LABEL: memset_zero_4: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: sw zero, 0(a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_4: +; RV64-FAST-LABEL: memset_zero_4: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: sw zero, 0(a0) ; RV64-FAST-NEXT: ret @@ -430,8 +430,8 @@ define void @bzero_4(ptr %a) nounwind { ret void } -define void @bzero_8(ptr %a) nounwind { -; RV32-LABEL: bzero_8: +define void @memset_zero_8(ptr %a) nounwind { +; RV32-LABEL: memset_zero_8: ; RV32: # %bb.0: ; RV32-NEXT: sb zero, 4(a0) ; RV32-NEXT: sb zero, 5(a0) @@ -443,7 +443,7 @@ define void @bzero_8(ptr %a) nounwind { ; RV32-NEXT: sb zero, 3(a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_8: +; RV64-LABEL: memset_zero_8: ; RV64: # %bb.0: ; RV64-NEXT: sb zero, 4(a0) ; RV64-NEXT: sb zero, 5(a0) @@ -455,13 +455,13 @@ define void @bzero_8(ptr %a) nounwind { ; RV64-NEXT: sb zero, 3(a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_8: +; RV32-FAST-LABEL: memset_zero_8: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: sw zero, 0(a0) ; RV32-FAST-NEXT: sw zero, 4(a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_8: +; RV64-FAST-LABEL: memset_zero_8: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: sd zero, 0(a0) ; RV64-FAST-NEXT: ret @@ -469,29 +469,29 @@ define void @bzero_8(ptr %a) nounwind { ret void } -define void @bzero_16(ptr %a) nounwind { -; RV32-LABEL: bzero_16: +define void @memset_zero_16(ptr %a) nounwind { +; RV32-LABEL: memset_zero_16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_16: +; RV64-LABEL: memset_zero_16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: vse8.v v8, (a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_16: +; RV32-FAST-LABEL: memset_zero_16: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-FAST-NEXT: vmv.v.i v8, 0 ; RV32-FAST-NEXT: vse64.v v8, (a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_16: +; RV64-FAST-LABEL: memset_zero_16: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-FAST-NEXT: vmv.v.i v8, 0 @@ -501,8 +501,8 @@ define void @bzero_16(ptr %a) nounwind { ret void } -define void @bzero_32(ptr %a) nounwind { -; RV32-LABEL: bzero_32: +define void @memset_zero_32(ptr %a) nounwind { +; RV32-LABEL: memset_zero_32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vmv.v.i v8, 0 @@ -511,7 +511,7 @@ define void @bzero_32(ptr %a) nounwind { ; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_32: +; RV64-LABEL: memset_zero_32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vmv.v.i v8, 0 @@ -520,7 +520,7 @@ define void @bzero_32(ptr %a) nounwind { ; RV64-NEXT: vse8.v v8, (a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_32: +; RV32-FAST-LABEL: memset_zero_32: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-FAST-NEXT: vmv.v.i v8, 0 @@ -529,7 +529,7 @@ define void @bzero_32(ptr %a) nounwind { ; RV32-FAST-NEXT: vse64.v v8, (a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_32: +; RV64-FAST-LABEL: memset_zero_32: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-FAST-NEXT: vmv.v.i v8, 0 @@ -541,8 +541,8 @@ define void @bzero_32(ptr %a) nounwind { ret void } -define void @bzero_64(ptr %a) nounwind { -; RV32-LABEL: bzero_64: +define void @memset_zero_64(ptr %a) nounwind { +; RV32-LABEL: memset_zero_64: ; RV32: # %bb.0: ; RV32-NEXT: li a1, 64 ; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma @@ -550,7 +550,7 @@ define void @bzero_64(ptr %a) nounwind { ; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: ret ; -; RV64-LABEL: bzero_64: +; RV64-LABEL: memset_zero_64: ; RV64: # %bb.0: ; RV64-NEXT: li a1, 64 ; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma @@ -558,14 +558,14 @@ define void @bzero_64(ptr %a) nounwind { ; RV64-NEXT: vse8.v v8, (a0) ; RV64-NEXT: ret ; -; RV32-FAST-LABEL: bzero_64: +; RV32-FAST-LABEL: memset_zero_64: ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV32-FAST-NEXT: vmv.v.i v8, 0 ; RV32-FAST-NEXT: vse64.v v8, (a0) ; RV32-FAST-NEXT: ret ; -; RV64-FAST-LABEL: bzero_64: +; RV64-FAST-LABEL: memset_zero_64: ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-FAST-NEXT: vmv.v.i v8, 0 @@ -577,13 +577,13 @@ define void @bzero_64(ptr %a) nounwind { ; ///////////////////////////////////////////////////////////////////////////// -define void @aligned_bzero_2(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_2: +define void @aligned_memset_zero_2(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_2: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sh zero, 0(a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_2: +; RV64-BOTH-LABEL: aligned_memset_zero_2: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sh zero, 0(a0) ; RV64-BOTH-NEXT: ret @@ -591,13 +591,13 @@ define void @aligned_bzero_2(ptr %a) nounwind { ret void } -define void @aligned_bzero_4(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_4: +define void @aligned_memset_zero_4(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_4: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sw zero, 0(a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_4: +; RV64-BOTH-LABEL: aligned_memset_zero_4: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sw zero, 0(a0) ; RV64-BOTH-NEXT: ret @@ -605,14 +605,14 @@ define void @aligned_bzero_4(ptr %a) nounwind { ret void } -define void @aligned_bzero_8(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_8: +define void @aligned_memset_zero_8(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_8: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sw zero, 0(a0) ; RV32-BOTH-NEXT: sw zero, 4(a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_8: +; RV64-BOTH-LABEL: aligned_memset_zero_8: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sd zero, 0(a0) ; RV64-BOTH-NEXT: ret @@ -621,15 +621,15 @@ define void @aligned_bzero_8(ptr %a) nounwind { } -define void @aligned_bzero_16(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_16: +define void @aligned_memset_zero_16(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_16: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-BOTH-NEXT: vmv.v.i v8, 0 ; RV32-BOTH-NEXT: vse64.v v8, (a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_16: +; RV64-BOTH-LABEL: aligned_memset_zero_16: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-BOTH-NEXT: vmv.v.i v8, 0 @@ -639,8 +639,8 @@ define void @aligned_bzero_16(ptr %a) nounwind { ret void } -define void @aligned_bzero_32(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_32: +define void @aligned_memset_zero_32(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_32: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-BOTH-NEXT: vmv.v.i v8, 0 @@ -649,7 +649,7 @@ define void @aligned_bzero_32(ptr %a) nounwind { ; RV32-BOTH-NEXT: vse64.v v8, (a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_32: +; RV64-BOTH-LABEL: aligned_memset_zero_32: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-BOTH-NEXT: vmv.v.i v8, 0 @@ -661,15 +661,15 @@ define void @aligned_bzero_32(ptr %a) nounwind { ret void } -define void @aligned_bzero_64(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_64: +define void @aligned_memset_zero_64(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_64: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV32-BOTH-NEXT: vmv.v.i v8, 0 ; RV32-BOTH-NEXT: vse64.v v8, (a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_64: +; RV64-BOTH-LABEL: aligned_memset_zero_64: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-BOTH-NEXT: vmv.v.i v8, 0 @@ -679,8 +679,8 @@ define void @aligned_bzero_64(ptr %a) nounwind { ret void } -define void @aligned_bzero_66(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_66: +define void @aligned_memset_zero_66(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_66: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: sh zero, 64(a0) ; RV32-BOTH-NEXT: vsetivli zero, 8, e64, m4, ta, ma @@ -688,7 +688,7 @@ define void @aligned_bzero_66(ptr %a) nounwind { ; RV32-BOTH-NEXT: vse64.v v8, (a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_66: +; RV64-BOTH-LABEL: aligned_memset_zero_66: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: sh zero, 64(a0) ; RV64-BOTH-NEXT: vsetivli zero, 8, e64, m4, ta, ma @@ -699,8 +699,8 @@ define void @aligned_bzero_66(ptr %a) nounwind { ret void } -define void @aligned_bzero_96(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_96: +define void @aligned_memset_zero_96(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_96: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV32-BOTH-NEXT: vmv.v.i v8, 0 @@ -713,7 +713,7 @@ define void @aligned_bzero_96(ptr %a) nounwind { ; RV32-BOTH-NEXT: vse64.v v8, (a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_96: +; RV64-BOTH-LABEL: aligned_memset_zero_96: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-BOTH-NEXT: vmv.v.i v8, 0 @@ -729,15 +729,15 @@ define void @aligned_bzero_96(ptr %a) nounwind { ret void } -define void @aligned_bzero_128(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_128: +define void @aligned_memset_zero_128(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_128: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV32-BOTH-NEXT: vmv.v.i v8, 0 ; RV32-BOTH-NEXT: vse64.v v8, (a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_128: +; RV64-BOTH-LABEL: aligned_memset_zero_128: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-BOTH-NEXT: vmv.v.i v8, 0 @@ -747,8 +747,8 @@ define void @aligned_bzero_128(ptr %a) nounwind { ret void } -define void @aligned_bzero_256(ptr %a) nounwind { -; RV32-BOTH-LABEL: aligned_bzero_256: +define void @aligned_memset_zero_256(ptr %a) nounwind { +; RV32-BOTH-LABEL: aligned_memset_zero_256: ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV32-BOTH-NEXT: vmv.v.i v8, 0 @@ -757,7 +757,7 @@ define void @aligned_bzero_256(ptr %a) nounwind { ; RV32-BOTH-NEXT: vse64.v v8, (a0) ; RV32-BOTH-NEXT: ret ; -; RV64-BOTH-LABEL: aligned_bzero_256: +; RV64-BOTH-LABEL: aligned_memset_zero_256: ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-BOTH-NEXT: vmv.v.i v8, 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll index 1e2e779..2f2035b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll @@ -222,3 +222,14 @@ define <vscale x 1 x i64> @vleff_move_past_passthru(ptr %p, ptr %q, iXLen %avl) %b = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %vec, iXLen %avl) ret <vscale x 1 x i64> %b } + +define <vscale x 1 x i64> @vmerge(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, <vscale x 1 x i1> %m, iXLen %avl) { +; CHECK-LABEL: vmerge: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma +; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0 +; CHECK-NEXT: ret + %a = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.nxv1i64(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, <vscale x 1 x i1> %m, iXLen %avl) + %b = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %a, iXLen %avl) + ret <vscale x 1 x i64> %b +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir index 6e106e5..9c3e96d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir @@ -152,3 +152,19 @@ body: | %y:gpr = ADDI $x0, 1 %z:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 0 /* tu, mu */ ... +--- +name: vmerge_vvm +body: | + bb.0: + liveins: $v8, $v0 + ; CHECK-LABEL: name: vmerge_vvm + ; CHECK: liveins: $v8, $v0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %x:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, $noreg, %mask, 4, 5 /* e32 */ + %passthru:vr = COPY $v8 + %mask:vmv0 = COPY $v0 + %x:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %passthru, $noreg, %mask, 4, 5 /* e32 */ + %z:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 0 /* tu, mu */ +... diff --git a/llvm/test/CodeGen/RISCV/xmips-cbop.ll b/llvm/test/CodeGen/RISCV/xmips-cbop.ll index cbbd1de..0d5defc 100644 --- a/llvm/test/CodeGen/RISCV/xmips-cbop.ll +++ b/llvm/test/CodeGen/RISCV/xmips-cbop.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32XMIPSPREFETCH -; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64XMIPSPREFETCH define void @prefetch_data_read(ptr noundef %ptr) nounwind { @@ -49,3 +49,54 @@ define void @prefetch_inst_read(ptr noundef %ptr) nounwind { tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 0, i32 0, i32 0) ret void } + +define void @prefetch_frameindex_test_neg() nounwind { +; RV32XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg: +; RV32XMIPSPREFETCH: # %bb.0: +; RV32XMIPSPREFETCH-NEXT: lui a0, 1 +; RV32XMIPSPREFETCH-NEXT: addi a0, a0, 16 +; RV32XMIPSPREFETCH-NEXT: sub sp, sp, a0 +; RV32XMIPSPREFETCH-NEXT: addi a0, sp, 524 +; RV32XMIPSPREFETCH-NEXT: mips.pref 8, 0(a0) +; RV32XMIPSPREFETCH-NEXT: lui a0, 1 +; RV32XMIPSPREFETCH-NEXT: addi a0, a0, 16 +; RV32XMIPSPREFETCH-NEXT: add sp, sp, a0 +; RV32XMIPSPREFETCH-NEXT: ret +; +; RV64XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg: +; RV64XMIPSPREFETCH: # %bb.0: +; RV64XMIPSPREFETCH-NEXT: lui a0, 1 +; RV64XMIPSPREFETCH-NEXT: addi a0, a0, 16 +; RV64XMIPSPREFETCH-NEXT: sub sp, sp, a0 +; RV64XMIPSPREFETCH-NEXT: addi a0, sp, 524 +; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 0(a0) +; RV64XMIPSPREFETCH-NEXT: lui a0, 1 +; RV64XMIPSPREFETCH-NEXT: addi a0, a0, 16 +; RV64XMIPSPREFETCH-NEXT: add sp, sp, a0 +; RV64XMIPSPREFETCH-NEXT: ret + %data = alloca [1024 x i32], align 4 + %ptr = getelementptr [1024 x i32], ptr %data, i32 0, i32 127 + call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1) + ret void +} + +define void @prefetch_frameindex_test() nounwind { +; RV32XMIPSPREFETCH-LABEL: prefetch_frameindex_test: +; RV32XMIPSPREFETCH: # %bb.0: +; RV32XMIPSPREFETCH-NEXT: addi sp, sp, -512 +; RV32XMIPSPREFETCH-NEXT: mips.pref 8, 32(sp) +; RV32XMIPSPREFETCH-NEXT: addi sp, sp, 512 +; RV32XMIPSPREFETCH-NEXT: ret +; +; RV64XMIPSPREFETCH-LABEL: prefetch_frameindex_test: +; RV64XMIPSPREFETCH: # %bb.0: +; RV64XMIPSPREFETCH-NEXT: addi sp, sp, -512 +; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 32(sp) +; RV64XMIPSPREFETCH-NEXT: addi sp, sp, 512 +; RV64XMIPSPREFETCH-NEXT: ret + %data = alloca [128 x i32], align 4 + %base = bitcast ptr %data to ptr + %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 8 + call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1) + ret void +} |