diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV/half-convert.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/half-convert.ll | 60 |
1 files changed, 21 insertions, 39 deletions
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll index c53237e..facb544 100644 --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -4388,17 +4388,11 @@ define half @fcvt_h_wu(i32 %a) nounwind { } define half @fcvt_h_wu_load(ptr %p) nounwind { -; RV32IZFH-LABEL: fcvt_h_wu_load: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: lw a0, 0(a0) -; RV32IZFH-NEXT: fcvt.h.wu fa0, a0 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_h_wu_load: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: lwu a0, 0(a0) -; RV64IZFH-NEXT: fcvt.h.wu fa0, a0 -; RV64IZFH-NEXT: ret +; CHECKIZFH-LABEL: fcvt_h_wu_load: +; CHECKIZFH: # %bb.0: +; CHECKIZFH-NEXT: lw a0, 0(a0) +; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0 +; CHECKIZFH-NEXT: ret ; ; RV32IDZFH-LABEL: fcvt_h_wu_load: ; RV32IDZFH: # %bb.0: @@ -4408,33 +4402,21 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; ; RV64IDZFH-LABEL: fcvt_h_wu_load: ; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: lwu a0, 0(a0) +; RV64IDZFH-NEXT: lw a0, 0(a0) ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0 ; RV64IDZFH-NEXT: ret ; -; RV32IZHINX-LABEL: fcvt_h_wu_load: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: lw a0, 0(a0) -; RV32IZHINX-NEXT: fcvt.h.wu a0, a0 -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_h_wu_load: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: lwu a0, 0(a0) -; RV64IZHINX-NEXT: fcvt.h.wu a0, a0 -; RV64IZHINX-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_wu_load: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: lw a0, 0(a0) -; RV32IZDINXZHINX-NEXT: fcvt.h.wu a0, a0 -; RV32IZDINXZHINX-NEXT: ret +; CHECKIZHINX-LABEL: fcvt_h_wu_load: +; CHECKIZHINX: # %bb.0: +; CHECKIZHINX-NEXT: lw a0, 0(a0) +; CHECKIZHINX-NEXT: fcvt.h.wu a0, a0 +; CHECKIZHINX-NEXT: ret ; -; RV64IZDINXZHINX-LABEL: fcvt_h_wu_load: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: lwu a0, 0(a0) -; RV64IZDINXZHINX-NEXT: fcvt.h.wu a0, a0 -; RV64IZDINXZHINX-NEXT: ret +; CHECKIZDINXZHINX-LABEL: fcvt_h_wu_load: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: lw a0, 0(a0) +; CHECKIZDINXZHINX-NEXT: fcvt.h.wu a0, a0 +; CHECKIZDINXZHINX-NEXT: ret ; ; RV32I-LABEL: fcvt_h_wu_load: ; RV32I: # %bb.0: @@ -4476,7 +4458,7 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; RV64ID-LP64: # %bb.0: ; RV64ID-LP64-NEXT: addi sp, sp, -16 ; RV64ID-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-LP64-NEXT: lwu a0, 0(a0) +; RV64ID-LP64-NEXT: lw a0, 0(a0) ; RV64ID-LP64-NEXT: fcvt.s.wu fa5, a0 ; RV64ID-LP64-NEXT: fmv.x.w a0, fa5 ; RV64ID-LP64-NEXT: call __truncsfhf2 @@ -4505,7 +4487,7 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; RV64ID: # %bb.0: ; RV64ID-NEXT: addi sp, sp, -16 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64ID-NEXT: lwu a0, 0(a0) +; RV64ID-NEXT: lw a0, 0(a0) ; RV64ID-NEXT: fcvt.s.wu fa0, a0 ; RV64ID-NEXT: call __truncsfhf2 ; RV64ID-NEXT: fmv.x.w a0, fa0 @@ -4525,7 +4507,7 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; ; CHECK64-IZFHMIN-LABEL: fcvt_h_wu_load: ; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: lwu a0, 0(a0) +; CHECK64-IZFHMIN-NEXT: lw a0, 0(a0) ; CHECK64-IZFHMIN-NEXT: fcvt.s.wu fa5, a0 ; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 ; CHECK64-IZFHMIN-NEXT: ret @@ -4539,7 +4521,7 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; ; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu_load: ; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: lwu a0, 0(a0) +; CHECK64-IZHINXMIN-NEXT: lw a0, 0(a0) ; CHECK64-IZHINXMIN-NEXT: fcvt.s.wu a0, a0 ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECK64-IZHINXMIN-NEXT: ret @@ -4553,7 +4535,7 @@ define half @fcvt_h_wu_load(ptr %p) nounwind { ; ; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu_load: ; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: lwu a0, 0(a0) +; CHECK64-IZDINXZHINXMIN-NEXT: lw a0, 0(a0) ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 ; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECK64-IZDINXZHINXMIN-NEXT: ret |