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-rw-r--r--llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll66
1 files changed, 66 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll b/llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
new file mode 100644
index 0000000..b16672d3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
@@ -0,0 +1,66 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=CHECK,RV64
+
+define i1 @test1(i64 %x) {
+; RV32-LABEL: test1:
+; RV32: # %bb.0:
+; RV32-NEXT: slli a2, a1, 2
+; RV32-NEXT: srli a0, a0, 30
+; RV32-NEXT: srai a1, a1, 30
+; RV32-NEXT: or a0, a0, a2
+; RV32-NEXT: xori a0, a0, -2
+; RV32-NEXT: not a1, a1
+; RV32-NEXT: or a0, a0, a1
+; RV32-NEXT: seqz a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test1:
+; RV64: # %bb.0:
+; RV64-NEXT: srai a0, a0, 30
+; RV64-NEXT: addi a0, a0, 2
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: ret
+ %a = and i64 %x, -1073741824
+ %b = icmp eq i64 %a, -2147483648
+ ret i1 %b
+}
+
+define i1 @test2(i32 signext %x) {
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: srli a0, a0, 30
+; CHECK-NEXT: seqz a0, a0
+; CHECK-NEXT: ret
+ %a = and i32 %x, -1073741824
+ %b = icmp eq i32 %a, 0
+ ret i1 %b
+}
+
+define i1 @test3(i32 signext %x) {
+; CHECK-LABEL: test3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: srli a0, a0, 29
+; CHECK-NEXT: snez a0, a0
+; CHECK-NEXT: ret
+ %a = and i32 %x, -536870912
+ %b = icmp ne i32 %a, 0
+ ret i1 %b
+}
+
+define i1 @test4(i64 %x) {
+; RV32-LABEL: test4:
+; RV32: # %bb.0:
+; RV32-NEXT: srli a1, a1, 14
+; RV32-NEXT: seqz a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test4:
+; RV64: # %bb.0:
+; RV64-NEXT: srli a0, a0, 46
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: ret
+ %a = and i64 %x, -70368744177664
+ %b = icmp eq i64 %a, 0
+ ret i1 %b
+}