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-rw-r--r--llvm/test/CodeGen/AVR/bug-143247.ll4
-rw-r--r--llvm/test/CodeGen/AVR/half.ll534
-rw-r--r--llvm/test/CodeGen/AVR/issue-151080.ll95
-rw-r--r--llvm/test/CodeGen/AVR/llvm.sincos.ll70
-rw-r--r--llvm/test/CodeGen/AVR/load.ll36
-rw-r--r--llvm/test/CodeGen/AVR/shift.ll2
-rw-r--r--llvm/test/CodeGen/AVR/store.ll12
7 files changed, 703 insertions, 50 deletions
diff --git a/llvm/test/CodeGen/AVR/bug-143247.ll b/llvm/test/CodeGen/AVR/bug-143247.ll
index 07c4c65..d449327 100644
--- a/llvm/test/CodeGen/AVR/bug-143247.ll
+++ b/llvm/test/CodeGen/AVR/bug-143247.ll
@@ -8,18 +8,18 @@ define void @complex_sbi() {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: push r16
; CHECK-NEXT: push r17
-; CHECK-NEXT: ldi r24, 0
+; CHECK-NEXT: ldi r24, 1
; CHECK-NEXT: ldi r25, 0
; CHECK-NEXT: .LBB0_1: ; %while.cond
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: sbi 1, 7
-; CHECK-NEXT: adiw r24, 1
; CHECK-NEXT: movw r16, r24
; CHECK-NEXT: andi r24, 15
; CHECK-NEXT: andi r25, 0
; CHECK-NEXT: adiw r24, 1
; CHECK-NEXT: call nil
; CHECK-NEXT: movw r24, r16
+; CHECK-NEXT: adiw r24, 1
; CHECK-NEXT: rjmp .LBB0_1
entry:
br label %while.cond
diff --git a/llvm/test/CodeGen/AVR/half.ll b/llvm/test/CodeGen/AVR/half.ll
new file mode 100644
index 0000000..c922293
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/half.ll
@@ -0,0 +1,534 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc %s -o - -mtriple=avr | FileCheck %s
+
+; Tests for various operations on half precison float. Much of the test is
+; copied from test/CodeGen/X86/half.ll.
+
+define void @store(half %x, ptr %p) nounwind {
+; CHECK-LABEL: store:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov r30, r22
+; CHECK-NEXT: mov r31, r23
+; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: st Z, r24
+; CHECK-NEXT: ret
+ store half %x, ptr %p
+ ret void
+}
+
+define half @return(ptr %p) nounwind {
+; CHECK-LABEL: return:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: ld r24, Z
+; CHECK-NEXT: ldd r25, Z+1
+; CHECK-NEXT: ret
+ %r = load half, ptr %p
+ ret half %r
+}
+
+define dso_local double @loadd(ptr nocapture readonly %a) local_unnamed_addr nounwind {
+; CHECK-LABEL: loadd:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: ldd r24, Z+2
+; CHECK-NEXT: ldd r25, Z+3
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: rcall __extendsfdf2
+; CHECK-NEXT: ret
+entry:
+ %arrayidx = getelementptr inbounds i16, ptr %a, i64 1
+ %0 = load i16, ptr %arrayidx, align 2
+ %1 = tail call double @llvm.convert.from.fp16.f64(i16 %0)
+ ret double %1
+}
+
+define dso_local float @loadf(ptr nocapture readonly %a) local_unnamed_addr nounwind {
+; CHECK-LABEL: loadf:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: ldd r24, Z+2
+; CHECK-NEXT: ldd r25, Z+3
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: ret
+entry:
+ %arrayidx = getelementptr inbounds i16, ptr %a, i64 1
+ %0 = load i16, ptr %arrayidx, align 2
+ %1 = tail call float @llvm.convert.from.fp16.f32(i16 %0)
+ ret float %1
+}
+
+define dso_local void @stored(ptr nocapture %a, double %b) local_unnamed_addr nounwind {
+; CHECK-LABEL: stored:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: push r16
+; CHECK-NEXT: push r17
+; CHECK-NEXT: mov r30, r22
+; CHECK-NEXT: mov r31, r23
+; CHECK-NEXT: mov r22, r20
+; CHECK-NEXT: mov r23, r21
+; CHECK-NEXT: mov r20, r18
+; CHECK-NEXT: mov r21, r19
+; CHECK-NEXT: mov r18, r16
+; CHECK-NEXT: mov r19, r17
+; CHECK-NEXT: mov r16, r24
+; CHECK-NEXT: mov r17, r25
+; CHECK-NEXT: mov r24, r30
+; CHECK-NEXT: mov r25, r31
+; CHECK-NEXT: rcall __truncdfhf2
+; CHECK-NEXT: mov r30, r16
+; CHECK-NEXT: mov r31, r17
+; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: st Z, r24
+; CHECK-NEXT: pop r17
+; CHECK-NEXT: pop r16
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call i16 @llvm.convert.to.fp16.f64(double %b)
+ store i16 %0, ptr %a, align 2
+ ret void
+}
+
+define dso_local void @storef(ptr nocapture %a, float %b) local_unnamed_addr nounwind {
+; CHECK-LABEL: storef:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: push r16
+; CHECK-NEXT: push r17
+; CHECK-NEXT: mov r18, r22
+; CHECK-NEXT: mov r19, r23
+; CHECK-NEXT: mov r16, r24
+; CHECK-NEXT: mov r17, r25
+; CHECK-NEXT: mov r22, r20
+; CHECK-NEXT: mov r23, r21
+; CHECK-NEXT: mov r24, r18
+; CHECK-NEXT: mov r25, r19
+; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: mov r30, r16
+; CHECK-NEXT: mov r31, r17
+; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: st Z, r24
+; CHECK-NEXT: pop r17
+; CHECK-NEXT: pop r16
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call i16 @llvm.convert.to.fp16.f32(float %b)
+ store i16 %0, ptr %a, align 2
+ ret void
+}
+
+define void @test_load_store(ptr %in, ptr %out) nounwind {
+; CHECK-LABEL: test_load_store:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: ld r24, Z
+; CHECK-NEXT: ldd r25, Z+1
+; CHECK-NEXT: mov r30, r22
+; CHECK-NEXT: mov r31, r23
+; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: st Z, r24
+; CHECK-NEXT: ret
+ %val = load half, ptr %in
+ store half %val, ptr %out
+ ret void
+}
+
+define i16 @test_bitcast_from_half(ptr %addr) nounwind {
+; CHECK-LABEL: test_bitcast_from_half:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: ld r24, Z
+; CHECK-NEXT: ldd r25, Z+1
+; CHECK-NEXT: ret
+ %val = load half, ptr %addr
+ %val_int = bitcast half %val to i16
+ ret i16 %val_int
+}
+
+define void @test_bitcast_to_half(ptr %addr, i16 %in) nounwind {
+; CHECK-LABEL: test_bitcast_to_half:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: std Z+1, r23
+; CHECK-NEXT: st Z, r22
+; CHECK-NEXT: ret
+ %val_fp = bitcast i16 %in to half
+ store half %val_fp, ptr %addr
+ ret void
+}
+
+define half @from_bits(i16 %x) nounwind {
+; CHECK-LABEL: from_bits:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ret
+ %res = bitcast i16 %x to half
+ ret half %res
+}
+
+define i16 @to_bits(half %x) nounwind {
+; CHECK-LABEL: to_bits:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ret
+ %res = bitcast half %x to i16
+ ret i16 %res
+}
+
+define float @test_extend32(ptr %addr) nounwind {
+; CHECK-LABEL: test_extend32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: ld r24, Z
+; CHECK-NEXT: ldd r25, Z+1
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: ret
+ %val16 = load half, ptr %addr
+ %val32 = fpext half %val16 to float
+ ret float %val32
+}
+
+define double @test_extend64(ptr %addr) nounwind {
+; CHECK-LABEL: test_extend64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: ld r24, Z
+; CHECK-NEXT: ldd r25, Z+1
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: rcall __extendsfdf2
+; CHECK-NEXT: ret
+ %val16 = load half, ptr %addr
+ %val32 = fpext half %val16 to double
+ ret double %val32
+}
+
+define void @test_trunc32(float %in, ptr %addr) nounwind {
+; CHECK-LABEL: test_trunc32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: push r16
+; CHECK-NEXT: push r17
+; CHECK-NEXT: mov r16, r20
+; CHECK-NEXT: mov r17, r21
+; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: mov r30, r16
+; CHECK-NEXT: mov r31, r17
+; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: st Z, r24
+; CHECK-NEXT: pop r17
+; CHECK-NEXT: pop r16
+; CHECK-NEXT: ret
+ %val16 = fptrunc float %in to half
+ store half %val16, ptr %addr
+ ret void
+}
+
+define void @test_trunc64(double %in, ptr %addr) nounwind {
+; CHECK-LABEL: test_trunc64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: rcall __truncdfhf2
+; CHECK-NEXT: mov r30, r16
+; CHECK-NEXT: mov r31, r17
+; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: st Z, r24
+; CHECK-NEXT: ret
+ %val16 = fptrunc double %in to half
+ store half %val16, ptr %addr
+ ret void
+}
+
+define i64 @test_fptosi_i64(ptr %p) nounwind {
+; CHECK-LABEL: test_fptosi_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: ld r24, Z
+; CHECK-NEXT: ldd r25, Z+1
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: rcall __fixsfdi
+; CHECK-NEXT: ret
+ %a = load half, ptr %p, align 2
+ %r = fptosi half %a to i64
+ ret i64 %r
+}
+
+define void @test_sitofp_i64(i64 %a, ptr %p) nounwind {
+; CHECK-LABEL: test_sitofp_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: rcall __floatdisf
+; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: mov r30, r16
+; CHECK-NEXT: mov r31, r17
+; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: st Z, r24
+; CHECK-NEXT: ret
+ %r = sitofp i64 %a to half
+ store half %r, ptr %p
+ ret void
+}
+
+define i64 @test_fptoui_i64(ptr %p) nounwind {
+; CHECK-LABEL: test_fptoui_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: ld r24, Z
+; CHECK-NEXT: ldd r25, Z+1
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: rcall __fixunssfdi
+; CHECK-NEXT: ret
+ %a = load half, ptr %p, align 2
+ %r = fptoui half %a to i64
+ ret i64 %r
+}
+
+define void @test_uitofp_i64(i64 %a, ptr %p) nounwind {
+; CHECK-LABEL: test_uitofp_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: rcall __floatundisf
+; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: mov r30, r16
+; CHECK-NEXT: mov r31, r17
+; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: st Z, r24
+; CHECK-NEXT: ret
+ %r = uitofp i64 %a to half
+ store half %r, ptr %p
+ ret void
+}
+
+define <2 x float> @test_extend32_vec2(ptr %p) nounwind {
+; CHECK-LABEL: test_extend32_vec2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: push r12
+; CHECK-NEXT: push r13
+; CHECK-NEXT: push r14
+; CHECK-NEXT: push r15
+; CHECK-NEXT: push r16
+; CHECK-NEXT: push r17
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: ld r24, Z
+; CHECK-NEXT: ldd r25, Z+1
+; CHECK-NEXT: mov r12, r30
+; CHECK-NEXT: mov r13, r31
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: mov r16, r22
+; CHECK-NEXT: mov r17, r23
+; CHECK-NEXT: mov r14, r24
+; CHECK-NEXT: mov r15, r25
+; CHECK-NEXT: mov r30, r12
+; CHECK-NEXT: mov r31, r13
+; CHECK-NEXT: ldd r24, Z+2
+; CHECK-NEXT: ldd r25, Z+3
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: mov r18, r16
+; CHECK-NEXT: mov r19, r17
+; CHECK-NEXT: mov r20, r14
+; CHECK-NEXT: mov r21, r15
+; CHECK-NEXT: pop r17
+; CHECK-NEXT: pop r16
+; CHECK-NEXT: pop r15
+; CHECK-NEXT: pop r14
+; CHECK-NEXT: pop r13
+; CHECK-NEXT: pop r12
+; CHECK-NEXT: ret
+ %a = load <2 x half>, ptr %p, align 8
+ %b = fpext <2 x half> %a to <2 x float>
+ ret <2 x float> %b
+}
+
+define <1 x double> @test_extend64_vec1(ptr %p) nounwind {
+; CHECK-LABEL: test_extend64_vec1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov r30, r24
+; CHECK-NEXT: mov r31, r25
+; CHECK-NEXT: ld r24, Z
+; CHECK-NEXT: ldd r25, Z+1
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: rcall __extendsfdf2
+; CHECK-NEXT: ret
+ %a = load <1 x half>, ptr %p, align 8
+ %b = fpext <1 x half> %a to <1 x double>
+ ret <1 x double> %b
+}
+
+define void @test_trunc32_vec2(<2 x float> %a, ptr %p) nounwind {
+; CHECK-LABEL: test_trunc32_vec2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: push r12
+; CHECK-NEXT: push r13
+; CHECK-NEXT: push r14
+; CHECK-NEXT: push r15
+; CHECK-NEXT: mov r14, r20
+; CHECK-NEXT: mov r15, r21
+; CHECK-NEXT: mov r12, r18
+; CHECK-NEXT: mov r13, r19
+; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: mov r30, r16
+; CHECK-NEXT: mov r31, r17
+; CHECK-NEXT: std Z+3, r25
+; CHECK-NEXT: std Z+2, r24
+; CHECK-NEXT: mov r22, r12
+; CHECK-NEXT: mov r23, r13
+; CHECK-NEXT: mov r24, r14
+; CHECK-NEXT: mov r25, r15
+; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: mov r30, r16
+; CHECK-NEXT: mov r31, r17
+; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: st Z, r24
+; CHECK-NEXT: pop r15
+; CHECK-NEXT: pop r14
+; CHECK-NEXT: pop r13
+; CHECK-NEXT: pop r12
+; CHECK-NEXT: ret
+ %v = fptrunc <2 x float> %a to <2 x half>
+ store <2 x half> %v, ptr %p
+ ret void
+}
+
+define void @test_trunc64_vec1(<1 x double> %a, ptr %p) nounwind {
+; CHECK-LABEL: test_trunc64_vec1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: rcall __truncdfhf2
+; CHECK-NEXT: mov r30, r16
+; CHECK-NEXT: mov r31, r17
+; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: st Z, r24
+; CHECK-NEXT: ret
+ %v = fptrunc <1 x double> %a to <1 x half>
+ store <1 x half> %v, ptr %p
+ ret void
+}
+
+define float @test_sitofp_fadd_i32(i32 %a, ptr %b) nounwind {
+; CHECK-LABEL: test_sitofp_fadd_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: push r12
+; CHECK-NEXT: push r13
+; CHECK-NEXT: push r14
+; CHECK-NEXT: push r15
+; CHECK-NEXT: push r16
+; CHECK-NEXT: push r17
+; CHECK-NEXT: mov r16, r20
+; CHECK-NEXT: mov r17, r21
+; CHECK-NEXT: rcall __floatsisf
+; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: mov r14, r24
+; CHECK-NEXT: mov r15, r25
+; CHECK-NEXT: mov r30, r16
+; CHECK-NEXT: mov r31, r17
+; CHECK-NEXT: ld r24, Z
+; CHECK-NEXT: ldd r25, Z+1
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: mov r16, r22
+; CHECK-NEXT: mov r17, r23
+; CHECK-NEXT: mov r12, r24
+; CHECK-NEXT: mov r13, r25
+; CHECK-NEXT: mov r24, r14
+; CHECK-NEXT: mov r25, r15
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: mov r18, r22
+; CHECK-NEXT: mov r19, r23
+; CHECK-NEXT: mov r20, r24
+; CHECK-NEXT: mov r21, r25
+; CHECK-NEXT: mov r22, r16
+; CHECK-NEXT: mov r23, r17
+; CHECK-NEXT: mov r24, r12
+; CHECK-NEXT: mov r25, r13
+; CHECK-NEXT: rcall __addsf3
+; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: pop r17
+; CHECK-NEXT: pop r16
+; CHECK-NEXT: pop r15
+; CHECK-NEXT: pop r14
+; CHECK-NEXT: pop r13
+; CHECK-NEXT: pop r12
+; CHECK-NEXT: ret
+ %tmp0 = load half, ptr %b
+ %tmp1 = sitofp i32 %a to half
+ %tmp2 = fadd half %tmp0, %tmp1
+ %tmp3 = fpext half %tmp2 to float
+ ret float %tmp3
+}
+
+define half @chained_fp_ops(half %x) {
+; CHECK-LABEL: chained_fp_ops:
+; CHECK: ; %bb.0: ; %start
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: mov r18, r22
+; CHECK-NEXT: mov r19, r23
+; CHECK-NEXT: mov r20, r24
+; CHECK-NEXT: mov r21, r25
+; CHECK-NEXT: rcall __addsf3
+; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: ldi r18, 0
+; CHECK-NEXT: ldi r19, 0
+; CHECK-NEXT: ldi r20, 0
+; CHECK-NEXT: ldi r21, 63
+; CHECK-NEXT: rcall __mulsf3
+; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: ret
+start:
+ %y = fmul half %x, 0xH4000
+ %z = fdiv half %y, 0xH4000
+ ret half %z
+}
+
+define half @test_select_cc(half) nounwind {
+; CHECK-LABEL: test_select_cc:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: push r16
+; CHECK-NEXT: push r17
+; CHECK-NEXT: rcall __extendhfsf2
+; CHECK-NEXT: ldi r16, 0
+; CHECK-NEXT: ldi r17, 0
+; CHECK-NEXT: mov r18, r16
+; CHECK-NEXT: mov r19, r17
+; CHECK-NEXT: mov r20, r16
+; CHECK-NEXT: mov r21, r17
+; CHECK-NEXT: rcall __nesf2
+; CHECK-NEXT: cpi r24, 0
+; CHECK-NEXT: breq .LBB25_2
+; CHECK-NEXT: ; %bb.1:
+; CHECK-NEXT: ldi r16, 0
+; CHECK-NEXT: ldi r17, 60
+; CHECK-NEXT: .LBB25_2:
+; CHECK-NEXT: mov r24, r16
+; CHECK-NEXT: mov r25, r17
+; CHECK-NEXT: pop r17
+; CHECK-NEXT: pop r16
+; CHECK-NEXT: ret
+ %2 = fcmp une half %0, 0xH0000
+ %3 = uitofp i1 %2 to half
+ ret half %3
+}
+
+define half @fabs(half %x) nounwind {
+; CHECK-LABEL: fabs:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: andi r25, 127
+; CHECK-NEXT: ret
+ %a = call half @llvm.fabs.f16(half %x)
+ ret half %a
+}
+
+define half @fcopysign(half %x, half %y) nounwind {
+; CHECK-LABEL: fcopysign:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: andi r22, 0
+; CHECK-NEXT: andi r23, 128
+; CHECK-NEXT: andi r25, 127
+; CHECK-NEXT: or r24, r22
+; CHECK-NEXT: or r25, r23
+; CHECK-NEXT: ret
+ %a = call half @llvm.copysign.f16(half %x, half %y)
+ ret half %a
+}
diff --git a/llvm/test/CodeGen/AVR/issue-151080.ll b/llvm/test/CodeGen/AVR/issue-151080.ll
new file mode 100644
index 0000000..9829224
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/issue-151080.ll
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -O=3 -mtriple=avr-none -mcpu=attiny85 -verify-machineinstrs | FileCheck %s
+
+declare dso_local void @foo(i16 noundef) addrspace(1)
+@ci = dso_local global [30 x i16] zeroinitializer, align 1
+define void @loopreduce() {
+; CHECK-LABEL: loopreduce:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: push r14
+; CHECK-NEXT: push r15
+; CHECK-NEXT: push r16
+; CHECK-NEXT: push r17
+; CHECK-NEXT: ldi r26, lo8(ci)
+; CHECK-NEXT: ldi r27, hi8(ci)
+; CHECK-NEXT: ldi r16, lo8(ci+60)
+; CHECK-NEXT: ldi r17, hi8(ci+60)
+; CHECK-NEXT: .LBB0_1: ; %for.body
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld r24, X+
+; CHECK-NEXT: ld r25, X+
+; CHECK-NEXT: movw r14, r26
+; CHECK-NEXT: rcall foo
+; CHECK-NEXT: movw r26, r14
+; CHECK-NEXT: cp r26, r16
+; CHECK-NEXT: cpc r27, r17
+; CHECK-NEXT: brne .LBB0_1
+; CHECK-NEXT: ; %bb.2: ; %for.cond.cleanup
+; CHECK-NEXT: pop r17
+; CHECK-NEXT: pop r16
+; CHECK-NEXT: pop r15
+; CHECK-NEXT: pop r14
+; CHECK-NEXT: ret
+entry:
+ br label %for.body
+for.body: ; preds = %entry, %for.body
+ %i.03 = phi i16 [ 0, %entry ], [ %inc, %for.body ]
+ %arrayidx = getelementptr inbounds nuw [30 x i16], ptr @ci, i16 0, i16 %i.03
+ %0 = load i16, ptr %arrayidx, align 1
+ tail call addrspace(1) void @foo(i16 noundef %0)
+ %inc = add nuw nsw i16 %i.03, 1
+ %exitcond.not = icmp eq i16 %inc, 30
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+; Exit blocks
+for.cond.cleanup: ; preds = %for.body
+ ret void
+}
+
+define void @indvar() {
+; CHECK-LABEL: indvar:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: push r12
+; CHECK-NEXT: push r13
+; CHECK-NEXT: push r14
+; CHECK-NEXT: push r15
+; CHECK-NEXT: push r17
+; CHECK-NEXT: ldi r24, 8
+; CHECK-NEXT: ldi r25, 0
+; CHECK-NEXT: movw r14, r24
+; CHECK-NEXT: ldi r24, 1
+; CHECK-NEXT: ldi r25, 0
+; CHECK-NEXT: movw r12, r24
+; CHECK-NEXT: ldi r17, 3
+; CHECK-NEXT: .LBB1_1: ; %for.body
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: movw r24, r12
+; CHECK-NEXT: rcall foo
+; CHECK-NEXT: movw r22, r14
+; CHECK-NEXT: movw r24, r22
+; CHECK-NEXT: rcall __mulhi3
+; CHECK-NEXT: movw r30, r14
+; CHECK-NEXT: adiw r30, 1
+; CHECK-NEXT: movw r14, r30
+; CHECK-NEXT: cpi r24, -24
+; CHECK-NEXT: cpc r25, r17
+; CHECK-NEXT: brlo .LBB1_1
+; CHECK-NEXT: ; %bb.2: ; %for.cond.cleanup
+; CHECK-NEXT: pop r17
+; CHECK-NEXT: pop r15
+; CHECK-NEXT: pop r14
+; CHECK-NEXT: pop r13
+; CHECK-NEXT: pop r12
+; CHECK-NEXT: ret
+entry:
+ br label %for.body
+for.body: ; preds = %entry, %for.body
+ %i.03 = phi i16 [ 7, %entry ], [ %inc, %for.body ]
+ tail call addrspace(1) void @foo(i16 noundef 1)
+ %inc = add nuw nsw i16 %i.03, 1
+ %mul = mul nuw nsw i16 %inc, %inc
+ %cmp = icmp samesign ult i16 %mul, 1000
+ br i1 %cmp, label %for.body, label %for.cond.cleanup
+for.cond.cleanup: ; preds = %for.body
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/AVR/llvm.sincos.ll b/llvm/test/CodeGen/AVR/llvm.sincos.ll
index b70b8d3..ff01da9 100644
--- a/llvm/test/CodeGen/AVR/llvm.sincos.ll
+++ b/llvm/test/CodeGen/AVR/llvm.sincos.ll
@@ -11,8 +11,6 @@ define { half, half } @test_sincos_f16(half %a) #0 {
; CHECK-NEXT: push r15
; CHECK-NEXT: push r16
; CHECK-NEXT: push r17
-; CHECK-NEXT: mov r24, r22
-; CHECK-NEXT: mov r25, r23
; CHECK-NEXT: rcall __extendhfsf2
; CHECK-NEXT: mov r16, r22
; CHECK-NEXT: mov r17, r23
@@ -28,10 +26,8 @@ define { half, half } @test_sincos_f16(half %a) #0 {
; CHECK-NEXT: mov r25, r15
; CHECK-NEXT: rcall cos
; CHECK-NEXT: rcall __truncsfhf2
-; CHECK-NEXT: mov r22, r24
-; CHECK-NEXT: mov r23, r25
-; CHECK-NEXT: mov r18, r12
-; CHECK-NEXT: mov r19, r13
+; CHECK-NEXT: mov r22, r12
+; CHECK-NEXT: mov r23, r13
; CHECK-NEXT: pop r17
; CHECK-NEXT: pop r16
; CHECK-NEXT: pop r15
@@ -46,13 +42,9 @@ define { half, half } @test_sincos_f16(half %a) #0 {
define half @test_sincos_f16_only_use_sin(half %a) #0 {
; CHECK-LABEL: test_sincos_f16_only_use_sin:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov r24, r22
-; CHECK-NEXT: mov r25, r23
; CHECK-NEXT: rcall __extendhfsf2
; CHECK-NEXT: rcall sin
; CHECK-NEXT: rcall __truncsfhf2
-; CHECK-NEXT: mov r22, r24
-; CHECK-NEXT: mov r23, r25
; CHECK-NEXT: ret
%result = call { half, half } @llvm.sincos.f16(half %a)
%result.0 = extractvalue { half, half } %result, 0
@@ -62,13 +54,9 @@ define half @test_sincos_f16_only_use_sin(half %a) #0 {
define half @test_sincos_f16_only_use_cos(half %a) #0 {
; CHECK-LABEL: test_sincos_f16_only_use_cos:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov r24, r22
-; CHECK-NEXT: mov r25, r23
; CHECK-NEXT: rcall __extendhfsf2
; CHECK-NEXT: rcall cos
; CHECK-NEXT: rcall __truncsfhf2
-; CHECK-NEXT: mov r22, r24
-; CHECK-NEXT: mov r23, r25
; CHECK-NEXT: ret
%result = call { half, half } @llvm.sincos.f16(half %a)
%result.1 = extractvalue { half, half } %result, 1
@@ -90,48 +78,50 @@ define { <2 x half>, <2 x half> } @test_sincos_v2f16(<2 x half> %a) #0 {
; CHECK-NEXT: push r15
; CHECK-NEXT: push r16
; CHECK-NEXT: push r17
-; CHECK-NEXT: mov r10, r22
-; CHECK-NEXT: mov r11, r23
+; CHECK-NEXT: mov r16, r24
+; CHECK-NEXT: mov r17, r25
+; CHECK-NEXT: mov r24, r22
+; CHECK-NEXT: mov r25, r23
; CHECK-NEXT: rcall __extendhfsf2
-; CHECK-NEXT: mov r16, r22
-; CHECK-NEXT: mov r17, r23
-; CHECK-NEXT: mov r14, r24
-; CHECK-NEXT: mov r15, r25
-; CHECK-NEXT: rcall sin
-; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: mov r14, r22
+; CHECK-NEXT: mov r15, r23
; CHECK-NEXT: mov r12, r24
; CHECK-NEXT: mov r13, r25
-; CHECK-NEXT: mov r24, r10
-; CHECK-NEXT: mov r25, r11
+; CHECK-NEXT: rcall sin
+; CHECK-NEXT: rcall __truncsfhf2
+; CHECK-NEXT: mov r10, r24
+; CHECK-NEXT: mov r11, r25
+; CHECK-NEXT: mov r24, r16
+; CHECK-NEXT: mov r25, r17
; CHECK-NEXT: rcall __extendhfsf2
-; CHECK-NEXT: mov r10, r22
-; CHECK-NEXT: mov r11, r23
+; CHECK-NEXT: mov r16, r22
+; CHECK-NEXT: mov r17, r23
; CHECK-NEXT: mov r8, r24
; CHECK-NEXT: mov r9, r25
-; CHECK-NEXT: rcall cos
+; CHECK-NEXT: rcall sin
; CHECK-NEXT: rcall __truncsfhf2
; CHECK-NEXT: mov r6, r24
; CHECK-NEXT: mov r7, r25
-; CHECK-NEXT: mov r22, r10
-; CHECK-NEXT: mov r23, r11
-; CHECK-NEXT: mov r24, r8
-; CHECK-NEXT: mov r25, r9
-; CHECK-NEXT: rcall sin
+; CHECK-NEXT: mov r22, r14
+; CHECK-NEXT: mov r23, r15
+; CHECK-NEXT: mov r24, r12
+; CHECK-NEXT: mov r25, r13
+; CHECK-NEXT: rcall cos
; CHECK-NEXT: rcall __truncsfhf2
-; CHECK-NEXT: mov r10, r24
-; CHECK-NEXT: mov r11, r25
+; CHECK-NEXT: mov r14, r24
+; CHECK-NEXT: mov r15, r25
; CHECK-NEXT: mov r22, r16
; CHECK-NEXT: mov r23, r17
-; CHECK-NEXT: mov r24, r14
-; CHECK-NEXT: mov r25, r15
+; CHECK-NEXT: mov r24, r8
+; CHECK-NEXT: mov r25, r9
; CHECK-NEXT: rcall cos
; CHECK-NEXT: rcall __truncsfhf2
; CHECK-NEXT: mov r18, r10
; CHECK-NEXT: mov r19, r11
-; CHECK-NEXT: mov r20, r12
-; CHECK-NEXT: mov r21, r13
-; CHECK-NEXT: mov r22, r6
-; CHECK-NEXT: mov r23, r7
+; CHECK-NEXT: mov r20, r6
+; CHECK-NEXT: mov r21, r7
+; CHECK-NEXT: mov r22, r14
+; CHECK-NEXT: mov r23, r15
; CHECK-NEXT: pop r17
; CHECK-NEXT: pop r16
; CHECK-NEXT: pop r15
diff --git a/llvm/test/CodeGen/AVR/load.ll b/llvm/test/CodeGen/AVR/load.ll
index 5de6b48..6a1e067 100644
--- a/llvm/test/CodeGen/AVR/load.ll
+++ b/llvm/test/CodeGen/AVR/load.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6,sram < %s -mtriple=avr -verify-machineinstrs | FileCheck %s
+; RUN: llc -mattr=avr6,sram < %s -mtriple=avr-none -verify-machineinstrs | FileCheck %s
define i8 @load8(ptr %x) {
; CHECK-LABEL: load8:
@@ -98,9 +98,33 @@ while.end: ; preds = %while.body, %entry
ret i16 %r.0.lcssa
}
+define i16 @load16postincloopreduce(ptr %p, i16 %cnt) {
+; CHECK-LABEL: load16postincloopreduce:
+; CHECK: ld {{.*}}, {{[XYZ]}}+
+; CHECK: ld {{.*}}, {{[XYZ]}}+
+entry:
+ %cmp3 = icmp sgt i16 %cnt, 0
+ br i1 %cmp3, label %for.body, label %for.cond.cleanup
+for.cond.cleanup: ; preds = %for.body, %entry
+ %sum.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ]
+ ret i16 %sum.0.lcssa
+for.body: ; preds = %entry, %for.body
+ %i.06 = phi i16 [ %inc, %for.body ], [ 0, %entry ]
+ %sum.05 = phi i16 [ %add, %for.body ], [ 0, %entry ]
+ %p.addr.04 = phi ptr [ %incdec.ptr, %for.body ], [ %p, %entry ]
+ %incdec.ptr = getelementptr inbounds nuw i8, ptr %p.addr.04, i16 2
+ %0 = load i16, ptr %p.addr.04, align 1
+ %add = add nsw i16 %0, %sum.05
+ %inc = add nuw nsw i16 %i.06, 1
+ %exitcond.not = icmp eq i16 %inc, %cnt
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+}
+
define i8 @load8predec(ptr %x, i8 %y) {
; CHECK-LABEL: load8predec:
-; CHECK: ld {{.*}}, -{{[XYZ]}}
+; TODO: ld {{.*}}, -{{[XYZ]}}
+; CHECK: sbiw r26, 1
+; CHECK: ld {{.*}}, X
entry:
%tobool6 = icmp eq i8 %y, 0
br i1 %tobool6, label %while.end, label %while.body
@@ -121,8 +145,12 @@ while.end: ; preds = %while.body, %entry
define i16 @load16predec(ptr %x, i16 %y) {
; CHECK-LABEL: load16predec:
-; CHECK: ld {{.*}}, -{{[XYZ]}}
-; CHECK: ld {{.*}}, -{{[XYZ]}}
+; TODO: ld {{.*}}, -{{[XYZ]}}
+; TODO: ld {{.*}}, -{{[XYZ]}}
+; CHECK: sbiw r24, 2
+; CHECK: movw r30, r24
+; CHECK: ld {{.*}}, Z
+; CHECK: ldd {{.*}}, Z+1
entry:
%tobool2 = icmp eq i16 %y, 0
br i1 %tobool2, label %while.end, label %while.body
diff --git a/llvm/test/CodeGen/AVR/shift.ll b/llvm/test/CodeGen/AVR/shift.ll
index 9836f93..1bd9b45 100644
--- a/llvm/test/CodeGen/AVR/shift.ll
+++ b/llvm/test/CodeGen/AVR/shift.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=avr -mtriple=avr -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=avr-none -verify-machineinstrs | FileCheck %s
; Optimize for speed.
define i8 @shift_i8_i8_speed(i8 %a, i8 %b) {
diff --git a/llvm/test/CodeGen/AVR/store.ll b/llvm/test/CodeGen/AVR/store.ll
index aab0270..9c41645 100644
--- a/llvm/test/CodeGen/AVR/store.ll
+++ b/llvm/test/CodeGen/AVR/store.ll
@@ -94,7 +94,9 @@ while.end: ; preds = %while.body, %entry
define void @store8predec(ptr %x, i8 %y) {
; CHECK-LABEL: store8predec:
-; CHECK: st -{{[XYZ]}}, {{.*}}
+; TODO: st -{{[XYZ]}}, {{.*}}
+; CHECK: sbiw r26, 1
+; CHECK: st X, {{.*}}
entry:
%tobool3 = icmp eq i8 %y, 0
br i1 %tobool3, label %while.end, label %while.body
@@ -112,8 +114,12 @@ while.end: ; preds = %while.body, %entry
define void @store16predec(ptr %x, i16 %y) {
; CHECK-LABEL: store16predec:
-; CHECK: st -{{[XYZ]}}, {{.*}}
-; CHECK: st -{{[XYZ]}}, {{.*}}
+; TODO: st -{{[XYZ]}}, {{.*}}
+; TODO: st -{{[XYZ]}}, {{.*}}
+; CHECK: sbiw r24, 2
+; CHECK: movw r30, r24
+; CHECK: std Z+1, {{.*}}
+; CHECK: st Z, {{.*}}
entry:
%tobool3 = icmp eq i16 %y, 0
br i1 %tobool3, label %while.end, label %while.body
generated by cgit v1.1 at 2025-08-11 05:16:29 +0000