diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Support/TargetParser.cpp | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCV.td | 31 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSubtarget.h | 1 |
4 files changed, 29 insertions, 22 deletions
diff --git a/llvm/lib/Support/TargetParser.cpp b/llvm/lib/Support/TargetParser.cpp index cd72c97..a7eccb6 100644 --- a/llvm/lib/Support/TargetParser.cpp +++ b/llvm/lib/Support/TargetParser.cpp @@ -278,6 +278,8 @@ bool checkCPUKind(CPUKind Kind, bool IsRV64) { bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) { if (Kind == CK_INVALID) return false; +#define TUNE_PROC(ENUM, NAME) if (Kind == CK_##ENUM) return true; +#include "llvm/Support/RISCVTargetParser.def" return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64; } @@ -288,18 +290,10 @@ CPUKind parseCPUKind(StringRef CPU) { .Default(CK_INVALID); } -StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64) { - return llvm::StringSwitch<StringRef>(TuneCPU) -#define TUNE_ALIAS(NAME, RV32, RV64) .Case(NAME, IsRV64 ? StringRef(RV64) : StringRef(RV32)) -#include "llvm/Support/RISCVTargetParser.def" - .Default(TuneCPU); -} - CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) { - TuneCPU = resolveTuneCPUAlias(TuneCPU, IsRV64); - return llvm::StringSwitch<CPUKind>(TuneCPU) #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM) +#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM) #include "llvm/Support/RISCVTargetParser.def" .Default(CK_INVALID); } @@ -321,7 +315,7 @@ void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit()) Values.emplace_back(C.Name); } -#define TUNE_ALIAS(NAME, RV32, RV64) Values.emplace_back(StringRef(NAME)); +#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME)); #include "llvm/Support/RISCVTargetParser.def" } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp index 9b69170..dd437da 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -97,10 +97,13 @@ namespace RISCVFeatures { void validate(const Triple &TT, const FeatureBitset &FeatureBits) { if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) report_fatal_error("RV64 target requires an RV64 CPU"); - if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit]) + if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit]) report_fatal_error("RV32 target requires an RV32 CPU"); if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) report_fatal_error("RV32E can't be enabled for an RV64 target"); + if (FeatureBits[RISCV::Feature32Bit] && + FeatureBits[RISCV::Feature64Bit]) + report_fatal_error("RV32 and RV64 can't be combined"); } llvm::Expected<std::unique_ptr<RISCVISAInfo>> diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index ba3dec2..83ae2f7 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -447,6 +447,10 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">, AssemblerPredicate<(all_of FeatureStdExtZicbop), "'Zicbop' (Cache-Block Prefetch Instructions)">; +// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from +// tuning CPU names. +def Feature32Bit + : SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">; def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, @@ -527,42 +531,47 @@ include "RISCVSchedSiFive7.td" // RISC-V processors supported. //===----------------------------------------------------------------------===// -def : ProcessorModel<"generic-rv32", NoSchedModel, []>; +def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>; def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; // Support generic for compatibility with other targets. The triple will be used // to change to the appropriate rv32/rv64 version. def : ProcessorModel<"generic", NoSchedModel, []>; -def : ProcessorModel<"rocket-rv32", RocketModel, []>; +def : ProcessorModel<"rocket-rv32", RocketModel, [Feature32Bit]>; def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>; +def : ProcessorModel<"rocket", RocketModel, []>; -def : ProcessorModel<"sifive-7-rv32", SiFive7Model, [], - [TuneSiFive7]>; -def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit], +def : ProcessorModel<"sifive-7-series", SiFive7Model, [], [TuneSiFive7]>; -def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM, +def : ProcessorModel<"sifive-e20", RocketModel, [Feature32Bit, + FeatureStdExtM, FeatureStdExtC]>; -def : ProcessorModel<"sifive-e21", RocketModel, [FeatureStdExtM, +def : ProcessorModel<"sifive-e21", RocketModel, [Feature32Bit, + FeatureStdExtM, FeatureStdExtA, FeatureStdExtC]>; -def : ProcessorModel<"sifive-e24", RocketModel, [FeatureStdExtM, +def : ProcessorModel<"sifive-e24", RocketModel, [Feature32Bit, + FeatureStdExtM, FeatureStdExtA, FeatureStdExtF, FeatureStdExtC]>; -def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM, +def : ProcessorModel<"sifive-e31", RocketModel, [Feature32Bit, + FeatureStdExtM, FeatureStdExtA, FeatureStdExtC]>; -def : ProcessorModel<"sifive-e34", RocketModel, [FeatureStdExtM, +def : ProcessorModel<"sifive-e34", RocketModel, [Feature32Bit, + FeatureStdExtM, FeatureStdExtA, FeatureStdExtF, FeatureStdExtC]>; -def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM, +def : ProcessorModel<"sifive-e76", SiFive7Model, [Feature32Bit, + FeatureStdExtM, FeatureStdExtA, FeatureStdExtF, FeatureStdExtC], diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 571b5a7..a4598c1 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -91,6 +91,7 @@ private: bool HasStdExtZicboz = false; bool HasStdExtZicbop = false; bool HasStdExtZmmul = false; + bool HasRV32 = false; bool HasRV64 = false; bool IsRV32E = false; bool EnableLinkerRelax = false; |