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-rw-r--r--llvm/lib/CodeGen/CodeGen.cpp4
-rw-r--r--llvm/lib/CodeGen/MachineScheduler.cpp330
-rw-r--r--llvm/lib/CodeGen/RegAllocBasic.cpp2
-rw-r--r--llvm/lib/CodeGen/RegAllocGreedy.cpp2
4 files changed, 245 insertions, 93 deletions
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index d69a24f..35df2a47 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -94,7 +94,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeModuloScheduleTestPass(Registry);
initializeMachinePostDominatorTreeWrapperPassPass(Registry);
initializeMachineRegionInfoPassPass(Registry);
- initializeMachineSchedulerPass(Registry);
+ initializeMachineSchedulerLegacyPass(Registry);
initializeMachineSinkingPass(Registry);
initializeMachineUniformityAnalysisPassPass(Registry);
initializeMachineUniformityInfoPrinterPassPass(Registry);
@@ -105,7 +105,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePHIEliminationPass(Registry);
initializePatchableFunctionPass(Registry);
initializePeepholeOptimizerLegacyPass(Registry);
- initializePostMachineSchedulerPass(Registry);
+ initializePostMachineSchedulerLegacyPass(Registry);
initializePostRAHazardRecognizerPass(Registry);
initializePostRAMachineSinkingPass(Registry);
initializePostRASchedulerLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 3f72e84..1be7a33 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -214,69 +214,119 @@ MachineSchedContext::~MachineSchedContext() {
delete RegClassInfo;
}
-namespace {
-
-/// Base class for a machine scheduler class that can run at any point.
-class MachineSchedulerBase : public MachineSchedContext,
- public MachineFunctionPass {
-public:
- MachineSchedulerBase(char &ID) : MachineFunctionPass(ID) {}
+namespace llvm {
+namespace impl_detail {
+/// Base class for the machine scheduler classes.
+class MachineSchedulerBase : public MachineSchedContext {
protected:
void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags);
};
-/// MachineScheduler runs after coalescing and before register allocation.
-class MachineScheduler : public MachineSchedulerBase {
-public:
- MachineScheduler();
+/// Impl class for MachineScheduler.
+class MachineSchedulerImpl : public MachineSchedulerBase {
+ // These are only for using MF.verify()
+ // remove when verify supports passing in all analyses
+ MachineFunctionPass *P = nullptr;
+ MachineFunctionAnalysisManager *MFAM = nullptr;
- void getAnalysisUsage(AnalysisUsage &AU) const override;
+public:
+ struct RequiredAnalyses {
+ MachineLoopInfo &MLI;
+ MachineDominatorTree &MDT;
+ AAResults &AA;
+ LiveIntervals &LIS;
+ };
- bool runOnMachineFunction(MachineFunction&) override;
+ MachineSchedulerImpl() {}
+ // Migration only
+ void setLegacyPass(MachineFunctionPass *P) { this->P = P; }
+ void setMFAM(MachineFunctionAnalysisManager *MFAM) { this->MFAM = MFAM; }
- static char ID; // Class identification, replacement for typeinfo
+ bool run(MachineFunction &MF, const TargetMachine &TM,
+ const RequiredAnalyses &Analyses);
protected:
ScheduleDAGInstrs *createMachineScheduler();
};
-/// PostMachineScheduler runs after shortly before code emission.
-class PostMachineScheduler : public MachineSchedulerBase {
+/// Impl class for PostMachineScheduler.
+class PostMachineSchedulerImpl : public MachineSchedulerBase {
+ // These are only for using MF.verify()
+ // remove when verify supports passing in all analyses
+ MachineFunctionPass *P = nullptr;
+ MachineFunctionAnalysisManager *MFAM = nullptr;
+
public:
- PostMachineScheduler();
+ struct RequiredAnalyses {
+ MachineLoopInfo &MLI;
+ AAResults &AA;
+ };
+ PostMachineSchedulerImpl() {}
+ // Migration only
+ void setLegacyPass(MachineFunctionPass *P) { this->P = P; }
+ void setMFAM(MachineFunctionAnalysisManager *MFAM) { this->MFAM = MFAM; }
- void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool run(MachineFunction &Func, const TargetMachine &TM,
+ const RequiredAnalyses &Analyses);
+
+protected:
+ ScheduleDAGInstrs *createPostMachineScheduler();
+};
+} // namespace impl_detail
+} // namespace llvm
+
+using impl_detail::MachineSchedulerBase;
+using impl_detail::MachineSchedulerImpl;
+using impl_detail::PostMachineSchedulerImpl;
+
+namespace {
+/// MachineScheduler runs after coalescing and before register allocation.
+class MachineSchedulerLegacy : public MachineFunctionPass {
+ MachineSchedulerImpl Impl;
+
+public:
+ MachineSchedulerLegacy();
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
bool runOnMachineFunction(MachineFunction&) override;
static char ID; // Class identification, replacement for typeinfo
+};
-protected:
- ScheduleDAGInstrs *createPostMachineScheduler();
+/// PostMachineScheduler runs after shortly before code emission.
+class PostMachineSchedulerLegacy : public MachineFunctionPass {
+ PostMachineSchedulerImpl Impl;
+
+public:
+ PostMachineSchedulerLegacy();
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ bool runOnMachineFunction(MachineFunction &) override;
+
+ static char ID; // Class identification, replacement for typeinfo
};
} // end anonymous namespace
-char MachineScheduler::ID = 0;
+char MachineSchedulerLegacy::ID = 0;
-char &llvm::MachineSchedulerID = MachineScheduler::ID;
+char &llvm::MachineSchedulerID = MachineSchedulerLegacy::ID;
-INITIALIZE_PASS_BEGIN(MachineScheduler, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(MachineSchedulerLegacy, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
-INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE,
+INITIALIZE_PASS_END(MachineSchedulerLegacy, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
-MachineScheduler::MachineScheduler() : MachineSchedulerBase(ID) {
- initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
+MachineSchedulerLegacy::MachineSchedulerLegacy() : MachineFunctionPass(ID) {
+ initializeMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry());
}
-void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
+void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -289,23 +339,24 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-char PostMachineScheduler::ID = 0;
+char PostMachineSchedulerLegacy::ID = 0;
-char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
+char &llvm::PostMachineSchedulerID = PostMachineSchedulerLegacy::ID;
-INITIALIZE_PASS_BEGIN(PostMachineScheduler, "postmisched",
+INITIALIZE_PASS_BEGIN(PostMachineSchedulerLegacy, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
-INITIALIZE_PASS_END(PostMachineScheduler, "postmisched",
+INITIALIZE_PASS_END(PostMachineSchedulerLegacy, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
-PostMachineScheduler::PostMachineScheduler() : MachineSchedulerBase(ID) {
- initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
+PostMachineSchedulerLegacy::PostMachineSchedulerLegacy()
+ : MachineFunctionPass(ID) {
+ initializePostMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry());
}
-void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
+void PostMachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -385,17 +436,14 @@ nextIfDebug(MachineBasicBlock::iterator I,
}
/// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
-ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
+ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
// Select the scheduler, or set the default.
MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
if (Ctor != useDefaultMachineSched)
return Ctor(this);
- const TargetMachine &TM =
- getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
-
// Get the default scheduler set by the target for this function.
- ScheduleDAGInstrs *Scheduler = TM.createMachineScheduler(this);
+ ScheduleDAGInstrs *Scheduler = TM->createMachineScheduler(this);
if (Scheduler)
return Scheduler;
@@ -403,14 +451,47 @@ ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
return createGenericSchedLive(this);
}
+bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM,
+ const RequiredAnalyses &Analyses) {
+ MF = &Func;
+ MLI = &Analyses.MLI;
+ MDT = &Analyses.MDT;
+ this->TM = &TM;
+ AA = &Analyses.AA;
+ LIS = &Analyses.LIS;
+
+ if (VerifyScheduling) {
+ LLVM_DEBUG(LIS->dump());
+ const char *MSchedBanner = "Before machine scheduling.";
+ if (P)
+ MF->verify(P, MSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, MSchedBanner, &errs());
+ }
+ RegClassInfo->runOnMachineFunction(*MF);
+
+ // Instantiate the selected scheduler for this target, function, and
+ // optimization level.
+ std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
+ scheduleRegions(*Scheduler, false);
+
+ LLVM_DEBUG(LIS->dump());
+ if (VerifyScheduling) {
+ const char *MSchedBanner = "After machine scheduling.";
+ if (P)
+ MF->verify(P, MSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, MSchedBanner, &errs());
+ }
+ return true;
+}
+
/// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
/// the caller. We don't have a command line option to override the postRA
/// scheduler. The Target must configure it.
-ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
- const TargetMachine &TM =
- getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() {
// Get the postRA scheduler set by the target for this function.
- ScheduleDAGInstrs *Scheduler = TM.createPostMachineScheduler(this);
+ ScheduleDAGInstrs *Scheduler = TM->createPostMachineScheduler(this);
if (Scheduler)
return Scheduler;
@@ -418,6 +499,37 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
return createGenericSchedPostRA(this);
}
+bool PostMachineSchedulerImpl::run(MachineFunction &Func,
+ const TargetMachine &TM,
+ const RequiredAnalyses &Analyses) {
+ MF = &Func;
+ MLI = &Analyses.MLI;
+ this->TM = &TM;
+ AA = &Analyses.AA;
+
+ if (VerifyScheduling) {
+ const char *PostMSchedBanner = "Before post machine scheduling.";
+ if (P)
+ MF->verify(P, PostMSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, PostMSchedBanner, &errs());
+ }
+
+ // Instantiate the selected scheduler for this target, function, and
+ // optimization level.
+ std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
+ scheduleRegions(*Scheduler, true);
+
+ if (VerifyScheduling) {
+ const char *PostMSchedBanner = "After post machine scheduling.";
+ if (P)
+ MF->verify(P, PostMSchedBanner, &errs());
+ else
+ MF->verify(*MFAM, PostMSchedBanner, &errs());
+ }
+ return true;
+}
+
/// Top-level MachineScheduler pass driver.
///
/// Visit blocks in function order. Divide each block into scheduling regions
@@ -434,72 +546,112 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
/// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
/// design would be to split blocks at scheduling boundaries, but LLVM has a
/// general bias against block splitting purely for implementation simplicity.
-bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
- if (skipFunction(mf.getFunction()))
+bool MachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
return false;
if (EnableMachineSched.getNumOccurrences()) {
if (!EnableMachineSched)
return false;
- } else if (!mf.getSubtarget().enableMachineScheduler())
+ } else if (!MF.getSubtarget().enableMachineScheduler()) {
return false;
-
- LLVM_DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs()));
-
- // Initialize the context of the pass.
- MF = &mf;
- MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
-
- LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
-
- if (VerifyScheduling) {
- LLVM_DEBUG(LIS->dump());
- MF->verify(this, "Before machine scheduling.", &errs());
}
- RegClassInfo->runOnMachineFunction(*MF);
- // Instantiate the selected scheduler for this target, function, and
- // optimization level.
- std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
- scheduleRegions(*Scheduler, false);
+ LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs()));
- LLVM_DEBUG(LIS->dump());
- if (VerifyScheduling)
- MF->verify(this, "After machine scheduling.", &errs());
- return true;
+ auto &MLI = getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ auto &TM = getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+ auto &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
+ auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+ Impl.setLegacyPass(this);
+ return Impl.run(MF, TM, {MLI, MDT, AA, LIS});
+}
+
+MachineSchedulerPass::MachineSchedulerPass(const TargetMachine *TM)
+ : Impl(std::make_unique<MachineSchedulerImpl>()), TM(TM) {}
+MachineSchedulerPass::~MachineSchedulerPass() = default;
+MachineSchedulerPass::MachineSchedulerPass(MachineSchedulerPass &&Other) =
+ default;
+
+PostMachineSchedulerPass::PostMachineSchedulerPass(const TargetMachine *TM)
+ : Impl(std::make_unique<PostMachineSchedulerImpl>()), TM(TM) {}
+PostMachineSchedulerPass::PostMachineSchedulerPass(
+ PostMachineSchedulerPass &&Other) = default;
+PostMachineSchedulerPass::~PostMachineSchedulerPass() = default;
+
+PreservedAnalyses
+MachineSchedulerPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ if (EnableMachineSched.getNumOccurrences()) {
+ if (!EnableMachineSched)
+ return PreservedAnalyses::all();
+ } else if (!MF.getSubtarget().enableMachineScheduler()) {
+ return PreservedAnalyses::all();
+ }
+
+ LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs()));
+ auto &MLI = MFAM.getResult<MachineLoopAnalysis>(MF);
+ auto &MDT = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+ auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+ .getManager();
+ auto &AA = FAM.getResult<AAManager>(MF.getFunction());
+ auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
+ Impl->setMFAM(&MFAM);
+ bool Changed = Impl->run(MF, *TM, {MLI, MDT, AA, LIS});
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<SlotIndexesAnalysis>();
+ PA.preserve<LiveIntervalsAnalysis>();
+ return PA;
}
-bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
- if (skipFunction(mf.getFunction()))
+bool PostMachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
return false;
if (EnablePostRAMachineSched.getNumOccurrences()) {
if (!EnablePostRAMachineSched)
return false;
- } else if (!mf.getSubtarget().enablePostRAMachineScheduler()) {
+ } else if (!MF.getSubtarget().enablePostRAMachineScheduler()) {
LLVM_DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
return false;
}
- LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
-
- // Initialize the context of the pass.
- MF = &mf;
- MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
-
- if (VerifyScheduling)
- MF->verify(this, "Before post machine scheduling.", &errs());
-
- // Instantiate the selected scheduler for this target, function, and
- // optimization level.
- std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
- scheduleRegions(*Scheduler, true);
+ LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; MF.print(dbgs()));
+ auto &MLI = getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ auto &TM = getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+ auto &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
+ Impl.setLegacyPass(this);
+ return Impl.run(MF, TM, {MLI, AA});
+}
- if (VerifyScheduling)
- MF->verify(this, "After post machine scheduling.", &errs());
- return true;
+PreservedAnalyses
+PostMachineSchedulerPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ if (EnablePostRAMachineSched.getNumOccurrences()) {
+ if (!EnablePostRAMachineSched)
+ return PreservedAnalyses::all();
+ } else if (!MF.getSubtarget().enablePostRAMachineScheduler()) {
+ LLVM_DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
+ return PreservedAnalyses::all();
+ }
+ LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; MF.print(dbgs()));
+ auto &MLI = MFAM.getResult<MachineLoopAnalysis>(MF);
+ auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+ .getManager();
+ auto &AA = FAM.getResult<AAManager>(MF.getFunction());
+
+ Impl->setMFAM(&MFAM);
+ bool Changed = Impl->run(MF, *TM, {MLI, AA});
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
}
/// Return true of the given instruction should not be included in a scheduling
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index e1f0540..51e047b 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -135,7 +135,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(RegisterCoalescerLegacy)
-INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
+INITIALIZE_PASS_DEPENDENCY(MachineSchedulerLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 465c4e8..2e43ad7 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -155,7 +155,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(RegisterCoalescerLegacy)
-INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
+INITIALIZE_PASS_DEPENDENCY(MachineSchedulerLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
generated by cgit v1.1 at 2025-08-03 01:30:31 +0000