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author | Philip Reames <preames@rivosinc.com> | 2024-07-23 08:48:28 -0700 |
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committer | GitHub <noreply@github.com> | 2024-07-23 08:48:28 -0700 |
commit | d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59 (patch) | |
tree | e01df0be9f24aaa69ff197062ca309a0dd2928f8 /llvm | |
parent | 0cf92b1a464e20a397cb64f463b2af6992125e1d (diff) | |
download | llvm-d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59.zip llvm-d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59.tar.gz llvm-d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59.tar.bz2 |
[RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (#99700)
This implements the __builtin_cpu_init and __builtin_cpu_supports
builtin routines based on the compiler runtime changes in
https://github.com/llvm/llvm-project/pull/85790.
This is inspired by https://github.com/llvm/llvm-project/pull/85786.
Major changes are a) a restriction in scope to only the builtins (which
have a much narrower user interface), and the avoidance of false
generality. This change deliberately only handles group 0 extensions
(which happen to be all defined ones today), and avoids the tblgen
changes from that review.
I don't have an environment in which I can actually test this, but @BeMg
has been kind enough to report that this appears to work as expected.
Before this can make it into a release, we need a change such as
https://github.com/llvm/llvm-project/pull/99958. The gcc docs claim that
cpu_support can be called by "normal" code without calling the cpu_init
routine because the init routine will have been called by a high
priority constructor. Our current compiler-rt mechanism does not do
this.
Diffstat (limited to 'llvm')
-rw-r--r-- | llvm/include/llvm/TargetParser/RISCVISAInfo.h | 4 | ||||
-rw-r--r-- | llvm/lib/TargetParser/RISCVISAInfo.cpp | 40 |
2 files changed, 44 insertions, 0 deletions
diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h b/llvm/include/llvm/TargetParser/RISCVISAInfo.h index d7a0801..d71ff17 100644 --- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h +++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h @@ -80,6 +80,10 @@ public: std::set<StringRef> &EnabledFeatureNames, StringMap<StringRef> &DescMap); + /// Return the bit position (in group 0) of __riscv_feature_bits. Returns + /// -1 if not supported. + static int getRISCVFeaturesBitPosition(StringRef Ext); + private: RISCVISAInfo(unsigned XLen) : XLen(XLen) {} diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index e6ddbb4..9f650b8 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -1020,3 +1020,43 @@ std::string RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) { return isExperimentalExtension(Name) ? "experimental-" + Name.str() : Name.str(); } + +struct RISCVExtBit { + const StringLiteral ext; + uint8_t bitpos; +}; + +/// Maps extensions with assigned bit positions within group 0 of +/// __riscv_features_bits to their respective bit position. At the +/// moment all extensions are within group 0. +constexpr static RISCVExtBit RISCVGroup0BitPositions[] = { + {"a", 0}, {"c", 2}, + {"d", 3}, {"f", 5}, + {"i", 8}, {"m", 12}, + {"v", 21}, {"zacas", 26}, + {"zba", 27}, {"zbb", 28}, + {"zbc", 29}, {"zbkb", 30}, + {"zbkc", 31}, {"zbkx", 32}, + {"zbs", 33}, {"zfa", 34}, + {"zfh", 35}, {"zfhmin", 36}, + {"zicboz", 37}, {"zicond", 38}, + {"zihintntl", 39}, {"zihintpause", 40}, + {"zknd", 41}, {"zkne", 42}, + {"zknh", 43}, {"zksed", 44}, + {"zksh", 45}, {"zkt", 46}, + {"ztso", 47}, {"zvbb", 48}, + {"zvbc", 49}, {"zvfh", 50}, + {"zvfhmin", 51}, {"zvkb", 52}, + {"zvkg", 53}, {"zvkned", 54}, + {"zvknha", 55}, {"zvknhb", 56}, + {"zvksed", 57}, {"zvksh", 58}, + {"zvkt", 59}}; +int RISCVISAInfo::getRISCVFeaturesBitPosition(StringRef Ext) { + // Note that this code currently accepts mixed case extension names, but + // does not handle extension versions at all. That's probably fine because + // there's only one extension version in the __riscv_feature_bits vector. + for (auto E : RISCVGroup0BitPositions) + if (E.ext.equals_insensitive(Ext)) + return E.bitpos; + return -1; +} |