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author | Alexis Engelke <engelke@in.tum.de> | 2024-06-21 08:30:03 +0000 |
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committer | Alexis Engelke <engelke@in.tum.de> | 2024-06-21 10:25:28 +0000 |
commit | cba4dfdd2fd0515821459b50947f4ec0d8b5c58a (patch) | |
tree | ad4484f1cc534f006b32370d0b3bc33d9015db19 /llvm | |
parent | 53a059ca76b0a6a0dff731e5acc7d51e5a62546c (diff) | |
download | llvm-cba4dfdd2fd0515821459b50947f4ec0d8b5c58a.zip llvm-cba4dfdd2fd0515821459b50947f4ec0d8b5c58a.tar.gz llvm-cba4dfdd2fd0515821459b50947f4ec0d8b5c58a.tar.bz2 |
[RegAllocFast] Use unsigned for operand indices
MachineInstr operand indices can be up 24 bits currently. Use unsigned
as consistent data type for operand indices instead of uint16_t.
Diffstat (limited to 'llvm')
-rw-r--r-- | llvm/lib/CodeGen/RegAllocFast.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index 09ce8c4..d936147 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -258,7 +258,7 @@ private: /// cannot be allocated. RegUnitSet UsedInInstr; RegUnitSet PhysRegUses; - SmallVector<uint16_t, 8> DefOperandIndexes; + SmallVector<unsigned, 8> DefOperandIndexes; // Register masks attached to the current instruction. SmallVector<const uint32_t *> RegMasks; @@ -1314,7 +1314,7 @@ void RegAllocFastImpl::findAndSortDefOperandIndexes(const MachineInstr &MI) { } } - llvm::sort(DefOperandIndexes, [&](uint16_t I0, uint16_t I1) { + llvm::sort(DefOperandIndexes, [&](unsigned I0, unsigned I1) { const MachineOperand &MO0 = MI.getOperand(I0); const MachineOperand &MO1 = MI.getOperand(I1); Register Reg0 = MO0.getReg(); @@ -1439,7 +1439,7 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) { while (ReArrangedImplicitOps) { ReArrangedImplicitOps = false; findAndSortDefOperandIndexes(MI); - for (uint16_t OpIdx : DefOperandIndexes) { + for (unsigned OpIdx : DefOperandIndexes) { MachineOperand &MO = MI.getOperand(OpIdx); LLVM_DEBUG(dbgs() << "Allocating " << MO << '\n'); Register Reg = MO.getReg(); |