[AArch64] Make Read Write System Registers Read Only

This patch makes the following System Registers Read Only:

 - CurrentEL
 - ICH_MISR_EL2
 - PMBIDR_EL1
 - PMSIDR_EL1

as found in:
https://developer.arm.com/docs/ddi0595/e/aarch64-system-registers

Relative line numbers were also added to the tests so we get more
informative error messages on failure.

Change-Id: I963b4f01ca5737b58f9e8e7abe9ca1d99e328758

10 files changed, 43 insertions, 29 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index c7dbd01..488b480 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -844,7 +844,7 @@ def : RWSysReg<"SP_EL2",             0b11, 0b110, 0b0100, 0b0001, 0b000>;
 def : RWSysReg<"SPSel",              0b11, 0b000, 0b0100, 0b0010, 0b000>;
 def : RWSysReg<"NZCV",               0b11, 0b011, 0b0100, 0b0010, 0b000>;
 def : RWSysReg<"DAIF",               0b11, 0b011, 0b0100, 0b0010, 0b001>;
-def : RWSysReg<"CurrentEL",          0b11, 0b000, 0b0100, 0b0010, 0b010>;
+def : ROSysReg<"CurrentEL",          0b11, 0b000, 0b0100, 0b0010, 0b010>;
 def : RWSysReg<"SPSR_irq",           0b11, 0b100, 0b0100, 0b0011, 0b000>;
 def : RWSysReg<"SPSR_abt",           0b11, 0b100, 0b0100, 0b0011, 0b001>;
 def : RWSysReg<"SPSR_und",           0b11, 0b100, 0b0100, 0b0011, 0b010>;
@@ -1184,7 +1184,7 @@ def : RWSysReg<"ICH_AP1R1_EL2",      0b11, 0b100, 0b1100, 0b1001, 0b001>;
 def : RWSysReg<"ICH_AP1R2_EL2",      0b11, 0b100, 0b1100, 0b1001, 0b010>;
 def : RWSysReg<"ICH_AP1R3_EL2",      0b11, 0b100, 0b1100, 0b1001, 0b011>;
 def : RWSysReg<"ICH_HCR_EL2",        0b11, 0b100, 0b1100, 0b1011, 0b000>;
-def : RWSysReg<"ICH_MISR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b010>;
+def : ROSysReg<"ICH_MISR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b010>;
 def : RWSysReg<"ICH_VMCR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b111>;
 def : RWSysReg<"ICH_LR0_EL2",        0b11, 0b100, 0b1100, 0b1100, 0b000>;
 def : RWSysReg<"ICH_LR1_EL2",        0b11, 0b100, 0b1100, 0b1100, 0b001>;
@@ -1258,7 +1258,7 @@ let Requires = [{ {AArch64::FeatureSPE} }] in {
 def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>;
 def : RWSysReg<"PMBPTR_EL1",    0b11, 0b000, 0b1001, 0b1010, 0b001>;
 def : RWSysReg<"PMBSR_EL1",     0b11, 0b000, 0b1001, 0b1010, 0b011>;
-def : RWSysReg<"PMBIDR_EL1",    0b11, 0b000, 0b1001, 0b1010, 0b111>;
+def : ROSysReg<"PMBIDR_EL1",    0b11, 0b000, 0b1001, 0b1010, 0b111>;
 def : RWSysReg<"PMSCR_EL2",     0b11, 0b100, 0b1001, 0b1001, 0b000>;
 def : RWSysReg<"PMSCR_EL12",    0b11, 0b101, 0b1001, 0b1001, 0b000>;
 def : RWSysReg<"PMSCR_EL1",     0b11, 0b000, 0b1001, 0b1001, 0b000>;
@@ -1267,7 +1267,7 @@ def : RWSysReg<"PMSIRR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b011>;
 def : RWSysReg<"PMSFCR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b100>;
 def : RWSysReg<"PMSEVFR_EL1",   0b11, 0b000, 0b1001, 0b1001, 0b101>;
 def : RWSysReg<"PMSLATFR_EL1",  0b11, 0b000, 0b1001, 0b1001, 0b110>;
-def : RWSysReg<"PMSIDR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b111>;
+def : ROSysReg<"PMSIDR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b111>;
 }
 
 // v8.2a "RAS extension" registers
diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s
index 19ed248..ae34555 100644
--- a/llvm/test/MC/AArch64/arm64-system-encoding.s
+++ b/llvm/test/MC/AArch64/arm64-system-encoding.s
@@ -88,7 +88,6 @@ foo:
   msr CPTR_EL2, x3
   msr CPTR_EL3, x3
   msr CSSELR_EL1, x3
-  msr CURRENTEL, x3
   msr DACR32_EL2, x3
   msr ESR_EL1, x3
   msr ESR_EL2, x3
@@ -168,7 +167,6 @@ foo:
 ; CHECK: msr CPTR_EL2, x3               ; encoding: [0x43,0x11,0x1c,0xd5]
 ; CHECK: msr CPTR_EL3, x3               ; encoding: [0x43,0x11,0x1e,0xd5]
 ; CHECK: msr CSSELR_EL1, x3             ; encoding: [0x03,0x00,0x1a,0xd5]
-; CHECK: msr CurrentEL, x3              ; encoding: [0x43,0x42,0x18,0xd5]
 ; CHECK: msr DACR32_EL2, x3             ; encoding: [0x03,0x30,0x1c,0xd5]
 ; CHECK: msr ESR_EL1, x3                ; encoding: [0x03,0x52,0x18,0xd5]
 ; CHECK: msr ESR_EL2, x3                ; encoding: [0x03,0x52,0x1c,0xd5]
@@ -219,6 +217,10 @@ foo:
 ; CHECK: msr  S0_0_C0_C0_0, x0          ; encoding: [0x00,0x00,0x00,0xd5]
 ; CHECK: msr  S1_2_C3_C4_5, x2          ; encoding: [0xa2,0x34,0x0a,0xd5]
 
+// Readonly system registers: writing to them gives an error
+  msr CURRENTEL, x3
+; CHECK-ERRORS: :[[@LINE-1]]:7: error: expected writable system register or pstate
+
   mrs x3, ACTLR_EL1
   mrs x3, ACTLR_EL2
   mrs x3, ACTLR_EL3
diff --git a/llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s b/llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s
index c1dbc22..25fff6a 100644
--- a/llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s
+++ b/llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s
@@ -1,6 +1,13 @@
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+spe < %s | FileCheck %s
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2>&1 | FileCheck --check-prefix=NO_SPE %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+spe       < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding                   < %s 2> %t | FileCheck --check-prefix=NO_SPE_OUT %s
+// RUN: FileCheck --check-prefix=NO_SPE %s < %t
+
+// NO_SPE_OUT-NOT: msr
+// NO_SPE_OUT-NOT: mrs
+// NO_SPE_OUT-NOT: psb
 
   psb csync
 // CHECK: psb csync              // encoding: [0x3f,0x22,0x03,0xd5]
@@ -9,7 +16,6 @@
   msr pmblimitr_el1, x0
   msr pmbptr_el1, x0
   msr pmbsr_el1, x0
-  msr pmbidr_el1, x0
   msr pmscr_el2, x0
   msr pmscr_el12, x0
   msr pmscr_el1, x0
@@ -18,11 +24,9 @@
   msr pmsfcr_el1, x0
   msr pmsevfr_el1, x0
   msr pmslatfr_el1, x0
-  msr pmsidr_el1, x0
 // CHECK:     msr PMBLIMITR_EL1, x0       // encoding: [0x00,0x9a,0x18,0xd5]
 // CHECK:     msr PMBPTR_EL1, x0          // encoding: [0x20,0x9a,0x18,0xd5]
 // CHECK:     msr PMBSR_EL1, x0           // encoding: [0x60,0x9a,0x18,0xd5]
-// CHECK:     msr PMBIDR_EL1, x0          // encoding: [0xe0,0x9a,0x18,0xd5]
 // CHECK:     msr PMSCR_EL2, x0           // encoding: [0x00,0x99,0x1c,0xd5]
 // CHECK:     msr PMSCR_EL12, x0          // encoding: [0x00,0x99,0x1d,0xd5]
 // CHECK:     msr PMSCR_EL1, x0           // encoding: [0x00,0x99,0x18,0xd5]
@@ -31,9 +35,6 @@
 // CHECK:     msr PMSFCR_EL1, x0          // encoding: [0x80,0x99,0x18,0xd5]
 // CHECK:     msr PMSEVFR_EL1, x0         // encoding: [0xa0,0x99,0x18,0xd5]
 // CHECK:     msr PMSLATFR_EL1, x0        // encoding: [0xc0,0x99,0x18,0xd5]
-// CHECK:     msr PMSIDR_EL1, x0          // encoding: [0xe0,0x99,0x18,0xd5]
-// NO_SPE: error: expected writable system register or pstate
-// NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
@@ -46,6 +47,15 @@
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 
+
+// Readonly system registers: writing to them gives an error
+  msr pmbidr_el1, x0
+  msr pmsidr_el1, x0
+// ERROR: :[[@LINE-2]]:7: error: expected writable system register or pstate
+// ERROR: :[[@LINE-2]]:7: error: expected writable system register or pstate
+// NO_SPE: :[[@LINE-4]]:7: error: expected writable system register or pstate
+// NO_SPE: :[[@LINE-4]]:7: error: expected writable system register or pstate
+
 mrs x0, pmblimitr_el1
   mrs x0, pmbptr_el1
   mrs x0, pmbsr_el1
diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
index 4c65b03..067acbf 100644
--- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s
+++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
@@ -3375,10 +3375,12 @@
         msr spsel, #-1
         msr spsel #-1
         msr daifclr, #16
-// CHECK-ERROR: [[@LINE-4]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]
-// CHECK-ERROR: [[@LINE-4]]:20: error: {{expected|immediate must be an}} integer in range [0, 15]
-// CHECK-ERROR: [[@LINE-4]]:{{9|19}}: error: {{too few operands for instruction|expected comma before next operand|unexpected token in argument list}}
-// CHECK-ERROR: [[@LINE-4]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]
+        msr CurrentEL, x12
+// CHECK-ERROR: [[@LINE-5]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]
+// CHECK-ERROR: [[@LINE-5]]:20: error: {{expected|immediate must be an}} integer in range [0, 15]
+// CHECK-ERROR: [[@LINE-5]]:{{9|19}}: error: {{too few operands for instruction|expected comma before next operand|unexpected token in argument list}}
+// CHECK-ERROR: [[@LINE-5]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]
+// CHECK-ERROR: [[@LINE-5]]:13: error: expected writable system register or pstate
 
         sys #8, c1, c2, #7, x9
         sys #3, c16, c2, #3, x10
diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s
index 6c0c16e..933f8b6 100644
--- a/llvm/test/MC/AArch64/basic-a64-instructions.s
+++ b/llvm/test/MC/AArch64/basic-a64-instructions.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 %s | FileCheck %s
   .globl _func
 
 // Check that the assembler can handle the documented syntax from the ARM ARM.
@@ -3804,7 +3804,6 @@ _func:
 	msr SPSel, x12
 	msr NZCV, x12
 	msr DAIF, x12
-	msr CurrentEL, x12
 	msr SPSR_irq, x12
 	msr SPSR_abt, x12
 	msr SPSR_und, x12
@@ -4058,7 +4057,6 @@ _func:
 // CHECK: msr      {{SPSel|SPSEL}}, x12                 // encoding: [0x0c,0x42,0x18,0xd5]
 // CHECK: msr      {{nzcv|NZCV}}, x12                  // encoding: [0x0c,0x42,0x1b,0xd5]
 // CHECK: msr      {{daif|DAIF}}, x12                  // encoding: [0x2c,0x42,0x1b,0xd5]
-// CHECK: msr      {{CurrentEL|CURRENTEL}}, x12             // encoding: [0x4c,0x42,0x18,0xd5]
 // CHECK: msr      {{SPSR_irq|SPSR_IRQ}}, x12              // encoding: [0x0c,0x43,0x1c,0xd5]
 // CHECK: msr      {{SPSR_abt|SPSR_ABT}}, x12              // encoding: [0x2c,0x43,0x1c,0xd5]
 // CHECK: msr      {{SPSR_und|SPSR_UND}}, x12              // encoding: [0x4c,0x43,0x1c,0xd5]
diff --git a/llvm/test/MC/AArch64/gicv3-regs-diagnostics.s b/llvm/test/MC/AArch64/gicv3-regs-diagnostics.s
index bc005b1..bcf00b9 100644
--- a/llvm/test/MC/AArch64/gicv3-regs-diagnostics.s
+++ b/llvm/test/MC/AArch64/gicv3-regs-diagnostics.s
@@ -35,6 +35,7 @@
         msr ich_vtr_el2, x8
         msr ich_eisr_el2, x22
         msr ich_elsr_el2, x8
+        msr ich_misr_el2, x10
 // CHECK: error: expected writable system register or pstate
 // CHECK-NEXT:         msr icc_iar1_el1, x16
 // CHECK-NEXT:             ^
@@ -59,3 +60,6 @@
 // CHECK-NEXT: error: expected writable system register or pstate
 // CHECK-NEXT:         msr ich_elsr_el2, x8
 // CHECK-NEXT:             ^
+// CHECK-NEXT: error: expected writable system register or pstate
+// CHECK-NEXT:         msr ich_misr_el2, x10
+// CHECK-NEXT:             ^
diff --git a/llvm/test/MC/AArch64/gicv3-regs.s b/llvm/test/MC/AArch64/gicv3-regs.s
index faa4a02..f311fc5 100644
--- a/llvm/test/MC/AArch64/gicv3-regs.s
+++ b/llvm/test/MC/AArch64/gicv3-regs.s
@@ -1,4 +1,4 @@
- // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding %s | FileCheck %s
 
         mrs x8, icc_iar1_el1
         mrs x26, icc_iar0_el1
@@ -143,7 +143,6 @@
         msr ich_ap1r2_el2, x14
         msr ich_ap1r3_el2, x13
         msr ich_hcr_el2, x1
-        msr ich_misr_el2, x10
         msr ich_vmcr_el2, x24
         msr ich_lr0_el2, x26
         msr ich_lr1_el2, x9
@@ -195,7 +194,6 @@
 // CHECK: msr      {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14         // encoding: [0x4e,0xc9,0x1c,0xd5]
 // CHECK: msr      {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13         // encoding: [0x6d,0xc9,0x1c,0xd5]
 // CHECK: msr      {{ich_hcr_el2|ICH_HCR_EL2}}, x1            // encoding: [0x01,0xcb,0x1c,0xd5]
-// CHECK: msr      {{ich_misr_el2|ICH_MISR_EL2}}, x10          // encoding: [0x4a,0xcb,0x1c,0xd5]
 // CHECK: msr      {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24          // encoding: [0xf8,0xcb,0x1c,0xd5]
 // CHECK: msr      {{ich_lr0_el2|ICH_LR0_EL2}}, x26           // encoding: [0x1a,0xcc,0x1c,0xd5]
 // CHECK: msr      {{ich_lr1_el2|ICH_LR1_EL2}}, x9            // encoding: [0x29,0xcc,0x1c,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.2a-statistical-profiling.txt b/llvm/test/MC/Disassembler/AArch64/armv8.2a-statistical-profiling.txt
index dd18b8f..2779270 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.2a-statistical-profiling.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.2a-statistical-profiling.txt
@@ -24,7 +24,7 @@
 # NO_SPE: msr S3_0_C9_C10_1, x0
 # CHECK: msr PMBSR_EL1, x0
 # NO_SPE: msr S3_0_C9_C10_3, x0
-# CHECK: msr PMBIDR_EL1, x0
+# CHECK: msr S3_0_C9_C10_7, x0
 # NO_SPE: msr S3_0_C9_C10_7, x0
 # CHECK: msr PMSCR_EL2, x0
 # NO_SPE: msr S3_4_C9_C9_0, x0
@@ -42,7 +42,7 @@
 # NO_SPE: msr S3_0_C9_C9_5, x0
 # CHECK: msr PMSLATFR_EL1, x0
 # NO_SPE: msr S3_0_C9_C9_6, x0
-# CHECK: msr PMSIDR_EL1, x0
+# CHECK: msr S3_0_C9_C9_7, x0
 # NO_SPE: msr S3_0_C9_C9_7, x0
 
 [0x00,0x9a,0x38,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index be1300a..8561970 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -3277,7 +3277,7 @@
 # CHECK: msr      {{SPSel|SPSEL}}, x12
 # CHECK: msr      {{nzcv|NZCV}}, x12
 # CHECK: msr      {{daif|DAIF}}, x12
-# CHECK: msr      {{CurrentEL|CURRENTEL}}, x12
+# CHECK: msr      S3_0_C4_C2_2, x12
 # CHECK: msr      {{SPSR_irq|SPSR_IRQ}}, x12
 # CHECK: msr      {{SPSR_abt|SPSR_ABT}}, x12
 # CHECK: msr      {{SPSR_und|SPSR_UND}}, x12
diff --git a/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt b/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt
index 5c97765..6eb2c77 100644
--- a/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt
+++ b/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt
@@ -178,7 +178,7 @@
 0x1 0xcb 0x1c 0xd5
 # CHECK: msr      {{ich_hcr_el2|ICH_HCR_EL2}}, x1
 0x4a 0xcb 0x1c 0xd5
-# CHECK: msr      {{ich_misr_el2|ICH_MISR_EL2}}, x10
+# CHECK: msr      S3_4_C12_C11_2, x10
 0xf8 0xcb 0x1c 0xd5
 # CHECK: msr      {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24
 0x1a 0xcc 0x1c 0xd5