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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-05-24 14:50:42 +0100 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-05-24 14:50:42 +0100 |
commit | 729fdb6bb656f30d7868251a06a6f4ab111e1335 (patch) | |
tree | 7f0dd117b0e02773a93b2be0b9b53c258972b550 /llvm | |
parent | 14304055e0d223a6dd224625b8fd128e6f711eb5 (diff) | |
download | llvm-729fdb6bb656f30d7868251a06a6f4ab111e1335.zip llvm-729fdb6bb656f30d7868251a06a6f4ab111e1335.tar.gz llvm-729fdb6bb656f30d7868251a06a6f4ab111e1335.tar.bz2 |
[DAG] visitFunnelShift - pull out repeated SDLoc.
Diffstat (limited to 'llvm')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8607b50..93d8663 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -10745,6 +10745,7 @@ SDValue DAGCombiner::visitFunnelShift(SDNode *N) { SDValue N2 = N->getOperand(2); bool IsFSHL = N->getOpcode() == ISD::FSHL; unsigned BitWidth = VT.getScalarSizeInBits(); + SDLoc DL(N); // fold (fshl N0, N1, 0) -> N0 // fold (fshr N0, N1, 0) -> N1 @@ -10764,8 +10765,8 @@ SDValue DAGCombiner::visitFunnelShift(SDNode *N) { // fold (fsh* N0, N1, c) -> (fsh* N0, N1, c % BitWidth) if (Cst->getAPIntValue().uge(BitWidth)) { uint64_t RotAmt = Cst->getAPIntValue().urem(BitWidth); - return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0, N1, - DAG.getConstant(RotAmt, SDLoc(N), ShAmtTy)); + return DAG.getNode(N->getOpcode(), DL, VT, N0, N1, + DAG.getConstant(RotAmt, DL, ShAmtTy)); } unsigned ShAmt = Cst->getZExtValue(); @@ -10777,13 +10778,13 @@ SDValue DAGCombiner::visitFunnelShift(SDNode *N) { // fold fshl(N0, undef_or_zero, C) -> shl(N0, C) // fold fshr(N0, undef_or_zero, C) -> shl(N0, BW-C) if (IsUndefOrZero(N0)) - return DAG.getNode(ISD::SRL, SDLoc(N), VT, N1, - DAG.getConstant(IsFSHL ? BitWidth - ShAmt : ShAmt, - SDLoc(N), ShAmtTy)); + return DAG.getNode( + ISD::SRL, DL, VT, N1, + DAG.getConstant(IsFSHL ? BitWidth - ShAmt : ShAmt, DL, ShAmtTy)); if (IsUndefOrZero(N1)) - return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, - DAG.getConstant(IsFSHL ? ShAmt : BitWidth - ShAmt, - SDLoc(N), ShAmtTy)); + return DAG.getNode( + ISD::SHL, DL, VT, N0, + DAG.getConstant(IsFSHL ? ShAmt : BitWidth - ShAmt, DL, ShAmtTy)); // fold (fshl ld1, ld0, c) -> (ld0[ofs]) iff ld0 and ld1 are consecutive. // fold (fshr ld1, ld0, c) -> (ld0[ofs]) iff ld0 and ld1 are consecutive. @@ -10832,18 +10833,19 @@ SDValue DAGCombiner::visitFunnelShift(SDNode *N) { if (isPowerOf2_32(BitWidth)) { APInt ModuloBits(N2.getScalarValueSizeInBits(), BitWidth - 1); if (IsUndefOrZero(N0) && !IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits)) - return DAG.getNode(ISD::SRL, SDLoc(N), VT, N1, N2); + return DAG.getNode(ISD::SRL, DL, VT, N1, N2); if (IsUndefOrZero(N1) && IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits)) - return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N2); + return DAG.getNode(ISD::SHL, DL, VT, N0, N2); } // fold (fshl N0, N0, N2) -> (rotl N0, N2) // fold (fshr N0, N0, N2) -> (rotr N0, N2) - // TODO: Investigate flipping this rotate if only one is legal, if funnel shift - // is legal as well we might be better off avoiding non-constant (BW - N2). + // TODO: Investigate flipping this rotate if only one is legal. + // If funnel shift is legal as well we might be better off avoiding + // non-constant (BW - N2). unsigned RotOpc = IsFSHL ? ISD::ROTL : ISD::ROTR; if (N0 == N1 && hasOperation(RotOpc, VT)) - return DAG.getNode(RotOpc, SDLoc(N), VT, N0, N2); + return DAG.getNode(RotOpc, DL, VT, N0, N2); // Simplify, based on bits shifted out of N0/N1. if (SimplifyDemandedBits(SDValue(N, 0))) |