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authorNikita Popov <npopov@redhat.com>2025-09-02 09:10:45 +0200
committerNikita Popov <npopov@redhat.com>2025-09-03 11:12:11 +0200
commitcd7f7cf5cca6fa425523a5af9fd42f82c6566ebf (patch)
treec8a427383e767538b1ea388984c00f451c48bd8f /llvm/test
parent73bed64433072338d11ebf770d6db99c2ce810aa (diff)
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Reapply [IR] Remove options to make scalable TypeSize access a warning (#156336)
Reapplying now that buildbot has picked up the new configuration that does not use -treat-scalable-fixed-error-as-warning. ----- This removes the `LLVM_ENABLE_STRICT_FIXED_SIZE_VECTORS` cmake option and the `-treat-scalable-fixed-error-as-warning` opt flag. We stopped treating these as warnings by default a long time ago (62f09d788f9fc540db12f3cfa2f98760071fca96), so I don't think it makes sense to retain these options at this point. Accessing a scalable TypeSize as fixed should always result in an error.
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir2
-rw-r--r--llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll2
-rw-r--r--llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll2
3 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir b/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir
index 4d8067e..61e3c73 100644
--- a/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir
+++ b/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir
@@ -1,4 +1,4 @@
-# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -mcpu=a64fx -aarch64-enable-pipeliner -pipeliner-max-mii=100 -pipeliner-enable-copytophi=0 -debug-only=pipeliner -run-pass=pipeliner -treat-scalable-fixed-error-as-warning 2>&1 | FileCheck %s
+# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -mcpu=a64fx -aarch64-enable-pipeliner -pipeliner-max-mii=100 -pipeliner-enable-copytophi=0 -debug-only=pipeliner -run-pass=pipeliner 2>&1 | FileCheck %s
# REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll b/llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
index 981ccdb..78325a1 100644
--- a/llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
+++ b/llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
@@ -5,7 +5,7 @@
; REQUIRES: asserts
; FIXME: Support TLI.expandUnalignedLoad()/TLI.expandUnalignedStore() for SVE.
-; CHECK-FIXME: LLVM ERROR: Invalid size request on a scalable vector.
+; CHECK-FIXME: LLVM ERROR: Cannot implicitly convert a scalable size to a fixed-width size in `TypeSize::operator ScalarTy()
define void @unaligned_nxv16i1(ptr %ldptr, ptr %stptr) {
; CHECK-LABEL: unaligned_nxv16i1:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
index a91d38a5..23ea84c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
@@ -3,7 +3,7 @@
; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -filetype=null < %s 2>&1 | FileCheck %s --check-prefix=SDAG
; SDAG: LLVM ERROR: Scalarization of scalable vectors is not supported.
; RUN: not --crash llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -filetype=null < %s 2>&1 | FileCheck %s --check-prefix=GISEL
-; GISEL: LLVM ERROR: Invalid size request on a scalable vector.
+; GISEL: LLVM ERROR: Cannot implicitly convert a scalable size to a fixed-width size in `TypeSize::operator ScalarTy()`
define void @buffer_store_nxv2i32(ptr addrspace(8) inreg %rsrc, i32 %offset) {
call void @llvm.amdgcn.raw.ptr.buffer.store.nxv2i32(<vscale x 2 x i32> poison, ptr addrspace(8) %rsrc, i32 %offset, i32 0, i32 0)