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| author | Jim Lin <jim@andestech.com> | 2025-07-25 11:29:17 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-25 11:29:17 +0800 |
| commit | 4e3266fb6e40dedf99e25693e02f358de998ae69 (patch) | |
| tree | 37f68fca85dc57bcf4f5fe14a01ae38e1c58f1b7 /llvm/test | |
| parent | b0dea47ae613b5d4167058ebef6b91b92dea8488 (diff) | |
| download | llvm-4e3266fb6e40dedf99e25693e02f358de998ae69.zip llvm-4e3266fb6e40dedf99e25693e02f358de998ae69.tar.gz llvm-4e3266fb6e40dedf99e25693e02f358de998ae69.tar.bz2 | |
[RISCV] Implement load/store support for XAndesBFHCvt (#150350)
We use `lh` to load 2 bytes from memory into a gpr, then mask this gpr
with -65536 to emulate nan-boxing behavior, and then the value in gpr is
moved to fpr using `fmv.w.x`.
To move the value back from fpr to gpr, we use `fmv.x.w` and finally,
`sh` is used to store the lower 2 bytes back to memory.
If zfh is enabled at the same time, we can just use flh/fsw to
load/store bf16 directly.
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/xandesbfhcvt.ll | 45 |
1 files changed, 43 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/RISCV/xandesbfhcvt.ll b/llvm/test/CodeGen/RISCV/xandesbfhcvt.ll index 854d0b6..72242f1 100644 --- a/llvm/test/CodeGen/RISCV/xandesbfhcvt.ll +++ b/llvm/test/CodeGen/RISCV/xandesbfhcvt.ll @@ -1,8 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+xandesbfhcvt -target-abi ilp32f \ -; RUN: -verify-machineinstrs < %s | FileCheck %s +; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,XANDESBFHCVT %s +; RUN: llc -mtriple=riscv32 -mattr=+zfh,+xandesbfhcvt -target-abi ilp32f \ +; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZFH %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesbfhcvt -target-abi lp64f \ -; RUN: -verify-machineinstrs < %s | FileCheck %s +; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,XANDESBFHCVT %s +; RUN: llc -mtriple=riscv64 -mattr=+zfh,+xandesbfhcvt -target-abi lp64f \ +; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZFH %s define float @fcvt_s_bf16(bfloat %a) nounwind { ; CHECK-LABEL: fcvt_s_bf16: @@ -21,3 +25,40 @@ define bfloat @fcvt_bf16_s(float %a) nounwind { %1 = fptrunc float %a to bfloat ret bfloat %1 } + +; Check load and store to bf16. +define void @loadstorebf16(ptr %bf, ptr %sf) nounwind { +; XANDESBFHCVT-LABEL: loadstorebf16: +; XANDESBFHCVT: # %bb.0: # %entry +; XANDESBFHCVT-NEXT: lhu a2, 0(a0) +; XANDESBFHCVT-NEXT: lui a3, 1048560 +; XANDESBFHCVT-NEXT: or a2, a2, a3 +; XANDESBFHCVT-NEXT: fmv.w.x fa5, a2 +; XANDESBFHCVT-NEXT: nds.fcvt.s.bf16 fa5, fa5 +; XANDESBFHCVT-NEXT: fsw fa5, 0(a1) +; XANDESBFHCVT-NEXT: flw fa5, 0(a1) +; XANDESBFHCVT-NEXT: nds.fcvt.bf16.s fa5, fa5 +; XANDESBFHCVT-NEXT: fmv.x.w a1, fa5 +; XANDESBFHCVT-NEXT: sh a1, 0(a0) +; XANDESBFHCVT-NEXT: ret +; +; ZFH-LABEL: loadstorebf16: +; ZFH: # %bb.0: # %entry +; ZFH-NEXT: flh fa5, 0(a0) +; ZFH-NEXT: nds.fcvt.s.bf16 fa5, fa5 +; ZFH-NEXT: fsw fa5, 0(a1) +; ZFH-NEXT: flw fa5, 0(a1) +; ZFH-NEXT: nds.fcvt.bf16.s fa5, fa5 +; ZFH-NEXT: fsh fa5, 0(a0) +; ZFH-NEXT: ret +entry: + %0 = load bfloat, bfloat* %bf, align 2 + %1 = fpext bfloat %0 to float + store volatile float %1, float* %sf, align 4 + + %2 = load float, float* %sf, align 4 + %3 = fptrunc float %2 to bfloat + store volatile bfloat %3, bfloat* %bf, align 2 + + ret void +} |