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| author | Himadhith <79003240+Himadhith@users.noreply.github.com> | 2025-09-01 10:17:14 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-01 10:17:14 +0530 |
| commit | 09350bd1c5ebba6cae96afcb70ef8ac097f7e1de (patch) | |
| tree | c4f35fd70b61b8d0747c1b35fe643bd4e166c118 /llvm/test/MC/RISCV/large-instructions.test | |
| parent | 3fc1aad65bc38d964b81091e57b1bcb3d56b8a3c (diff) | |
| download | llvm-09350bd1c5ebba6cae96afcb70ef8ac097f7e1de.zip llvm-09350bd1c5ebba6cae96afcb70ef8ac097f7e1de.tar.gz llvm-09350bd1c5ebba6cae96afcb70ef8ac097f7e1de.tar.bz2 | |
[NFC][PowerPC] adding the arguments for register names and VSR to VR (#155991)
NFC patch to add the flags `-ppc-asm-full-reg-names
--ppc-vsr-nums-as-vr` to the test file
`llvm/test/CodeGen/PowerPC/check-zero-vector.ll`.
Created this PR based on this discussion:
https://github.com/llvm/llvm-project/pull/151971#issuecomment-3234090675
Co-authored-by: himadhith <himadhith.v@ibm.com>
Co-authored-by: Lei Huang <lei@ca.ibm.com>
Diffstat (limited to 'llvm/test/MC/RISCV/large-instructions.test')
0 files changed, 0 insertions, 0 deletions