[NFC][PowerPC] adding the arguments for register names and VSR to VR (#155991)

NFC patch to add the flags `-ppc-asm-full-reg-names
--ppc-vsr-nums-as-vr` to the test file
`llvm/test/CodeGen/PowerPC/check-zero-vector.ll`.

Created this PR based on this discussion:
https://github.com/llvm/llvm-project/pull/151971#issuecomment-3234090675

Co-authored-by: himadhith <himadhith.v@ibm.com>
Co-authored-by: Lei Huang <lei@ca.ibm.com>

1 files changed, 60 insertions, 60 deletions

diff --git a/llvm/test/CodeGen/PowerPC/check-zero-vector.ll b/llvm/test/CodeGen/PowerPC/check-zero-vector.ll
index d8e66d6..0f7e0c7 100644
--- a/llvm/test/CodeGen/PowerPC/check-zero-vector.ll
+++ b/llvm/test/CodeGen/PowerPC/check-zero-vector.ll
@@ -1,12 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN:    < %s | FileCheck %s --check-prefix=POWERPC_64LE
+; RUN:     -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64LE
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix \
-; RUN:  < %s | FileCheck %s --check-prefix=POWERPC_64
+; RUN:     -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc-ibm-aix \
-; RUN:   < %s | FileCheck %s --check-prefix=POWERPC_32
+; RUN:     -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_32
 
 define i32 @test_Greater_than(ptr %colauths) {
 ; This testcase is for the special case of zero-vector comparisons.
@@ -14,71 +14,71 @@ define i32 @test_Greater_than(ptr %colauths) {
 ; This pattern is expected to be optimized in a future patch.
 ; POWERPC_64LE-LABEL: test_Greater_than:
 ; POWERPC_64LE:       # %bb.0: # %entry
-; POWERPC_64LE-NEXT:    lfd 0, 0(3)
-; POWERPC_64LE-NEXT:    xxlxor 35, 35, 35
-; POWERPC_64LE-NEXT:    li 4, 0
-; POWERPC_64LE-NEXT:    li 3, 4
-; POWERPC_64LE-NEXT:    xxswapd 34, 0
-; POWERPC_64LE-NEXT:    vcmpequh 2, 2, 3
-; POWERPC_64LE-NEXT:    xxlnor 34, 34, 34
-; POWERPC_64LE-NEXT:    vmrglh 3, 2, 2
-; POWERPC_64LE-NEXT:    vextuwrx 4, 4, 2
-; POWERPC_64LE-NEXT:    vextuwrx 3, 3, 3
-; POWERPC_64LE-NEXT:    clrlwi 4, 4, 31
-; POWERPC_64LE-NEXT:    rlwimi 4, 3, 1, 30, 30
-; POWERPC_64LE-NEXT:    mfvsrwz 3, 35
-; POWERPC_64LE-NEXT:    rlwimi 4, 3, 2, 29, 29
-; POWERPC_64LE-NEXT:    li 3, 12
-; POWERPC_64LE-NEXT:    vextuwrx 3, 3, 3
-; POWERPC_64LE-NEXT:    rlwimi 4, 3, 3, 28, 28
-; POWERPC_64LE-NEXT:    stb 4, -1(1)
-; POWERPC_64LE-NEXT:    lbz 3, -1(1)
-; POWERPC_64LE-NEXT:    popcntd 3, 3
+; POWERPC_64LE-NEXT:    lfd f0, 0(r3)
+; POWERPC_64LE-NEXT:    xxlxor v3, v3, v3
+; POWERPC_64LE-NEXT:    li r4, 0
+; POWERPC_64LE-NEXT:    li r3, 4
+; POWERPC_64LE-NEXT:    xxswapd v2, f0
+; POWERPC_64LE-NEXT:    vcmpequh v2, v2, v3
+; POWERPC_64LE-NEXT:    xxlnor v2, v2, v2
+; POWERPC_64LE-NEXT:    vmrglh v3, v2, v2
+; POWERPC_64LE-NEXT:    vextuwrx r4, r4, v2
+; POWERPC_64LE-NEXT:    vextuwrx r3, r3, v3
+; POWERPC_64LE-NEXT:    clrlwi r4, r4, 31
+; POWERPC_64LE-NEXT:    rlwimi r4, r3, 1, 30, 30
+; POWERPC_64LE-NEXT:    mfvsrwz r3, v3
+; POWERPC_64LE-NEXT:    rlwimi r4, r3, 2, 29, 29
+; POWERPC_64LE-NEXT:    li r3, 12
+; POWERPC_64LE-NEXT:    vextuwrx r3, r3, v3
+; POWERPC_64LE-NEXT:    rlwimi r4, r3, 3, 28, 28
+; POWERPC_64LE-NEXT:    stb r4, -1(r1)
+; POWERPC_64LE-NEXT:    lbz r3, -1(r1)
+; POWERPC_64LE-NEXT:    popcntd r3, r3
 ; POWERPC_64LE-NEXT:    blr
 ;
 ; POWERPC_64-LABEL: test_Greater_than:
 ; POWERPC_64:       # %bb.0: # %entry
-; POWERPC_64-NEXT:    lxsd 2, 0(3)
-; POWERPC_64-NEXT:    xxlxor 35, 35, 35
-; POWERPC_64-NEXT:    li 4, 12
-; POWERPC_64-NEXT:    li 3, 8
-; POWERPC_64-NEXT:    vcmpequh 2, 2, 3
-; POWERPC_64-NEXT:    xxlnor 34, 34, 34
-; POWERPC_64-NEXT:    vmrghh 2, 2, 2
-; POWERPC_64-NEXT:    vextuwlx 4, 4, 2
-; POWERPC_64-NEXT:    vextuwlx 3, 3, 2
-; POWERPC_64-NEXT:    clrlwi 4, 4, 31
-; POWERPC_64-NEXT:    rlwimi 4, 3, 1, 30, 30
-; POWERPC_64-NEXT:    mfvsrwz 3, 34
-; POWERPC_64-NEXT:    rlwimi 4, 3, 2, 29, 29
-; POWERPC_64-NEXT:    li 3, 0
-; POWERPC_64-NEXT:    vextuwlx 3, 3, 2
-; POWERPC_64-NEXT:    rlwimi 4, 3, 3, 28, 28
-; POWERPC_64-NEXT:    stb 4, -1(1)
-; POWERPC_64-NEXT:    lbz 3, -1(1)
-; POWERPC_64-NEXT:    popcntd 3, 3
+; POWERPC_64-NEXT:    lxsd v2, 0(r3)
+; POWERPC_64-NEXT:    xxlxor v3, v3, v3
+; POWERPC_64-NEXT:    li r4, 12
+; POWERPC_64-NEXT:    li r3, 8
+; POWERPC_64-NEXT:    vcmpequh v2, v2, v3
+; POWERPC_64-NEXT:    xxlnor v2, v2, v2
+; POWERPC_64-NEXT:    vmrghh v2, v2, v2
+; POWERPC_64-NEXT:    vextuwlx r4, r4, v2
+; POWERPC_64-NEXT:    vextuwlx r3, r3, v2
+; POWERPC_64-NEXT:    clrlwi r4, r4, 31
+; POWERPC_64-NEXT:    rlwimi r4, r3, 1, 30, 30
+; POWERPC_64-NEXT:    mfvsrwz r3, v2
+; POWERPC_64-NEXT:    rlwimi r4, r3, 2, 29, 29
+; POWERPC_64-NEXT:    li r3, 0
+; POWERPC_64-NEXT:    vextuwlx r3, r3, v2
+; POWERPC_64-NEXT:    rlwimi r4, r3, 3, 28, 28
+; POWERPC_64-NEXT:    stb r4, -1(r1)
+; POWERPC_64-NEXT:    lbz r3, -1(r1)
+; POWERPC_64-NEXT:    popcntd r3, r3
 ; POWERPC_64-NEXT:    blr
 ;
 ; POWERPC_32-LABEL: test_Greater_than:
 ; POWERPC_32:       # %bb.0: # %entry
-; POWERPC_32-NEXT:    li 4, 4
-; POWERPC_32-NEXT:    lxvwsx 1, 0, 3
-; POWERPC_32-NEXT:    xxlxor 35, 35, 35
-; POWERPC_32-NEXT:    lxvwsx 0, 3, 4
-; POWERPC_32-NEXT:    xxmrghw 34, 1, 0
-; POWERPC_32-NEXT:    vcmpequh 2, 2, 3
-; POWERPC_32-NEXT:    xxlnor 34, 34, 34
-; POWERPC_32-NEXT:    vmrghh 2, 2, 2
-; POWERPC_32-NEXT:    stxv 34, -32(1)
-; POWERPC_32-NEXT:    lwz 3, -20(1)
-; POWERPC_32-NEXT:    lwz 4, -24(1)
-; POWERPC_32-NEXT:    clrlwi 3, 3, 31
-; POWERPC_32-NEXT:    rlwimi 3, 4, 1, 30, 30
-; POWERPC_32-NEXT:    lwz 4, -28(1)
-; POWERPC_32-NEXT:    rlwimi 3, 4, 2, 29, 29
-; POWERPC_32-NEXT:    lwz 4, -32(1)
-; POWERPC_32-NEXT:    rlwimi 3, 4, 3, 28, 28
-; POWERPC_32-NEXT:    popcntw 3, 3
+; POWERPC_32-NEXT:    li r4, 4
+; POWERPC_32-NEXT:    lxvwsx vs1, 0, r3
+; POWERPC_32-NEXT:    xxlxor v3, v3, v3
+; POWERPC_32-NEXT:    lxvwsx vs0, r3, r4
+; POWERPC_32-NEXT:    xxmrghw v2, vs1, vs0
+; POWERPC_32-NEXT:    vcmpequh v2, v2, v3
+; POWERPC_32-NEXT:    xxlnor v2, v2, v2
+; POWERPC_32-NEXT:    vmrghh v2, v2, v2
+; POWERPC_32-NEXT:    stxv v2, -32(r1)
+; POWERPC_32-NEXT:    lwz r3, -20(r1)
+; POWERPC_32-NEXT:    lwz r4, -24(r1)
+; POWERPC_32-NEXT:    clrlwi r3, r3, 31
+; POWERPC_32-NEXT:    rlwimi r3, r4, 1, 30, 30
+; POWERPC_32-NEXT:    lwz r4, -28(r1)
+; POWERPC_32-NEXT:    rlwimi r3, r4, 2, 29, 29
+; POWERPC_32-NEXT:    lwz r4, -32(r1)
+; POWERPC_32-NEXT:    rlwimi r3, r4, 3, 28, 28
+; POWERPC_32-NEXT:    popcntw r3, r3
 ; POWERPC_32-NEXT:    blr
 entry:
   %0 = load <4 x i16>, ptr %colauths, align 2, !tbaa !5