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| author | Vladislav Dzhidzhoev <vdzhidzhoev@accesssoftek.com> | 2023-08-14 11:16:04 +0200 |
|---|---|---|
| committer | Vladislav Dzhidzhoev <vdzhidzhoev@accesssoftek.com> | 2023-09-20 18:22:54 +0200 |
| commit | fb8f59156f0f208f6192ed808fc223eda6c0e7ec (patch) | |
| tree | 9d43d4630eaef600c5b4aef78a5fe3e96177bd09 /llvm/lib | |
| parent | de018f5ca4b2598f6bbf7a27a1fb51935792c276 (diff) | |
| download | llvm-fb8f59156f0f208f6192ed808fc223eda6c0e7ec.zip llvm-fb8f59156f0f208f6192ed808fc223eda6c0e7ec.tar.gz llvm-fb8f59156f0f208f6192ed808fc223eda6c0e7ec.tar.bz2 | |
[AArch64][GlobalISel] Adopt dup(load) -> LD1R patterns from SelectionDAG
Follow-up of #65630.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrGISel.td | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td index 0f3ef23..b47605c 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td +++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td @@ -496,3 +496,20 @@ let AddedComplexity = 19 in { defm : VecROStoreLane64_0Pat<ro16, store, v4i16, i16, hsub, STRHroW, STRHroX>; defm : VecROStoreLane64_0Pat<ro32, store, v2i32, i32, ssub, STRSroW, STRSroX>; } + +def : Pat<(v8i8 (AArch64dup (i8 (load (am_indexed8 GPR64sp:$Rn))))), + (LD1Rv8b GPR64sp:$Rn)>; +def : Pat<(v16i8 (AArch64dup (i8 (load GPR64sp:$Rn)))), + (LD1Rv16b GPR64sp:$Rn)>; +def : Pat<(v4i16 (AArch64dup (i16 (load GPR64sp:$Rn)))), + (LD1Rv4h GPR64sp:$Rn)>; +def : Pat<(v8i16 (AArch64dup (i16 (load GPR64sp:$Rn)))), + (LD1Rv8h GPR64sp:$Rn)>; +def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))), + (LD1Rv2s GPR64sp:$Rn)>; +def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))), + (LD1Rv4s GPR64sp:$Rn)>; +def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))), + (LD1Rv2d GPR64sp:$Rn)>; +def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))), + (LD1Rv1d GPR64sp:$Rn)>; |