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| author | Kazu Hirata <kazu@google.com> | 2025-04-14 23:03:55 -0700 |
|---|---|---|
| committer | Kazu Hirata <kazu@google.com> | 2025-04-14 23:03:55 -0700 |
| commit | f46cea5b42ed4d05fd11dc1e693ddc6153769cde (patch) | |
| tree | ad695c488f9178e4e870bec252d911881489add3 /llvm/lib | |
| parent | 2538c607e903a1fe0cfcacd5732235cc8ff3adf7 (diff) | |
| download | llvm-f46cea5b42ed4d05fd11dc1e693ddc6153769cde.zip llvm-f46cea5b42ed4d05fd11dc1e693ddc6153769cde.tar.gz llvm-f46cea5b42ed4d05fd11dc1e693ddc6153769cde.tar.bz2 | |
Revert "[AMDGPU][GlobalISel] Properly handle lane op lowering for larger vector types (#132358)"
This reverts commit 62ef10a0f62c668e1fa7e357f56052f3364544c5.
Multiple buildbot failures have been reported:
https://github.com/llvm/llvm-project/pull/132358
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 5fcbf81..275d019 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -5580,7 +5580,6 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper, return false; LLT PartialResTy = LLT::scalar(SplitSize); - bool NeedsBitcast = false; if (Ty.isVector()) { LLT EltTy = Ty.getElementType(); unsigned EltSize = EltTy.getSizeInBits(); @@ -5589,10 +5588,8 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper, } else if (EltSize == 16 || EltSize == 32) { unsigned NElem = SplitSize / EltSize; PartialResTy = Ty.changeElementCount(ElementCount::getFixed(NElem)); - } else { - // Handle all other cases via S32/S64 pieces - NeedsBitcast = true; } + // Handle all other cases via S32/S64 pieces; } SmallVector<Register, 4> PartialRes; @@ -5618,12 +5615,7 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper, PartialRes.push_back(createLaneOp(Src0, Src1, Src2, PartialResTy)); } - if (NeedsBitcast) - B.buildBitcast(DstReg, B.buildMergeLikeInstr( - LLT::scalar(Ty.getSizeInBits()), PartialRes)); - else - B.buildMergeLikeInstr(DstReg, PartialRes); - + B.buildMergeLikeInstr(DstReg, PartialRes); MI.eraseFromParent(); return true; } |