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| author | Paul Walker <paul.walker@arm.com> | 2020-08-10 19:02:02 +0100 |
|---|---|---|
| committer | Paul Walker <paul.walker@arm.com> | 2020-08-13 12:35:47 +0100 |
| commit | e63cc8105adfd452aebd079d2c0b2e915bcbc6d5 (patch) | |
| tree | 942659046ab2f3fd7221a826a4bd4ed06f4294ac /llvm/lib | |
| parent | 30af595f05b5c1cd39f148f00e71db2b91eb3036 (diff) | |
| download | llvm-e63cc8105adfd452aebd079d2c0b2e915bcbc6d5.zip llvm-e63cc8105adfd452aebd079d2c0b2e915bcbc6d5.tar.gz llvm-e63cc8105adfd452aebd079d2c0b2e915bcbc6d5.tar.bz2 | |
[SVE] Lower fixed length vector integer shifts.
Differential Revision: https://reviews.llvm.org/D85724
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index cb11564f..4cf2559 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1107,8 +1107,11 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) { setOperationAction(ISD::MUL, VT, Custom); setOperationAction(ISD::OR, VT, Custom); setOperationAction(ISD::SETCC, VT, Custom); + setOperationAction(ISD::SHL, VT, Custom); setOperationAction(ISD::SIGN_EXTEND, VT, Custom); setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); + setOperationAction(ISD::SRA, VT, Custom); + setOperationAction(ISD::SRL, VT, Custom); setOperationAction(ISD::STORE, VT, Custom); setOperationAction(ISD::SUB, VT, Custom); setOperationAction(ISD::TRUNCATE, VT, Custom); @@ -9053,7 +9056,7 @@ SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op, llvm_unreachable("unexpected shift opcode"); case ISD::SHL: - if (VT.isScalableVector()) + if (VT.isScalableVector() || useSVEForFixedLengthVectorVT(VT)) return LowerToPredicatedOp(Op, DAG, AArch64ISD::SHL_PRED); if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) @@ -9065,7 +9068,7 @@ SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op, Op.getOperand(0), Op.getOperand(1)); case ISD::SRA: case ISD::SRL: - if (VT.isScalableVector()) { + if (VT.isScalableVector() || useSVEForFixedLengthVectorVT(VT)) { unsigned Opc = Op.getOpcode() == ISD::SRA ? AArch64ISD::SRA_PRED : AArch64ISD::SRL_PRED; return LowerToPredicatedOp(Op, DAG, Opc); |