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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-09-02 17:16:51 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-02 17:16:51 +0900 |
| commit | e09fe9b5aae753c34827c71eea04284c20ed38d3 (patch) | |
| tree | eaa3cc9c6405957e7cf0a05bf81addf602fbf25c /llvm/lib | |
| parent | 1cdb8810ce66b79ff1f6efcf72a01ee9ae0d1c5f (diff) | |
| download | llvm-e09fe9b5aae753c34827c71eea04284c20ed38d3.zip llvm-e09fe9b5aae753c34827c71eea04284c20ed38d3.tar.gz llvm-e09fe9b5aae753c34827c71eea04284c20ed38d3.tar.bz2 | |
AMDGPU: Fix adding m0 uses to gfx12 ds atomics (#156399)
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/DSInstructions.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index 37031331..611695b 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -774,10 +774,10 @@ def DS_BVH_STACK_PUSH8_POP2_RTN_B64 : DS_BVH_STACK< "ds_bvh_stack_push8_pop2_rtn_b64", VReg_64, VReg_256>; } // End OtherPredicates = [HasImageInsts]. -defm DS_COND_SUB_U32 : DS_1A1D_NORET_mc<"ds_cond_sub_u32">; -defm DS_COND_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_cond_sub_rtn_u32", VGPR_32>; -defm DS_SUB_CLAMP_U32 : DS_1A1D_NORET_mc<"ds_sub_clamp_u32">; -defm DS_SUB_CLAMP_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_clamp_rtn_u32", VGPR_32>; +defm DS_COND_SUB_U32 : DS_1A1D_NORET_mc_gfx9<"ds_cond_sub_u32">; +defm DS_COND_SUB_RTN_U32 : DS_1A1D_RET_mc_gfx9<"ds_cond_sub_rtn_u32", VGPR_32>; +defm DS_SUB_CLAMP_U32 : DS_1A1D_NORET_mc_gfx9<"ds_sub_clamp_u32">; +defm DS_SUB_CLAMP_RTN_U32 : DS_1A1D_RET_mc_gfx9<"ds_sub_clamp_rtn_u32", VGPR_32>; def DS_BPERMUTE_FI_B32 : DS_1A1D_PERMUTE <"ds_bpermute_fi_b32", int_amdgcn_ds_bpermute_fi_b32>; |