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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-02-06 16:29:38 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-02-06 16:29:38 +0000 |
| commit | d3f966c6f02f4438d35ade0f0e802739c0802e2d (patch) | |
| tree | 5867f79336e0dab1aaf11c2c6900c944b6a0ebc8 /llvm/lib | |
| parent | 20e212197a5d84f02da14b567d43ae16d46fc643 (diff) | |
| download | llvm-d3f966c6f02f4438d35ade0f0e802739c0802e2d.zip llvm-d3f966c6f02f4438d35ade0f0e802739c0802e2d.tar.gz llvm-d3f966c6f02f4438d35ade0f0e802739c0802e2d.tar.bz2 | |
[AArch64] LowerVectorSRA_SRL_SHL - silence dead code warning
Remove default case from switch and move llvm_unreachable to after the switch()
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 4362bc0..f0813f1 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -11353,9 +11353,6 @@ SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op, unsigned EltSize = VT.getScalarSizeInBits(); switch (Op.getOpcode()) { - default: - llvm_unreachable("unexpected shift opcode"); - case ISD::SHL: if (VT.isScalableVector() || useSVEForFixedLengthVectorVT(VT)) return LowerToPredicatedOp(Op, DAG, AArch64ISD::SHL_PRED); @@ -11398,7 +11395,7 @@ SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op, return NegShiftLeft; } - return SDValue(); + llvm_unreachable("unexpected shift opcode"); } static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS, |