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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-07-25 05:47:09 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-25 05:47:09 +0530 |
| commit | d3937e2d12648caa49fd80f9520a391fde2f7ba5 (patch) | |
| tree | 9dc687383c8c32c7f5c1349b1f7615e167c9b371 /llvm/lib | |
| parent | 4ae26783724a8cb29b448920f5b4066ebbbf3a95 (diff) | |
| download | llvm-d3937e2d12648caa49fd80f9520a391fde2f7ba5.zip llvm-d3937e2d12648caa49fd80f9520a391fde2f7ba5.tar.gz llvm-d3937e2d12648caa49fd80f9520a391fde2f7ba5.tar.bz2 | |
[RISCV] Pass sign-extended value to isInt check in expandMul (#150211)
In the `isInt` check that was added in #147661 we were passing the
zero-extended `uint64_t` value instead of the sign-extended one.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 3918dd2..fa0196f 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -16079,7 +16079,7 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG, uint64_t MulAmt = CNode->getZExtValue(); // Don't do this if the Xqciac extension is enabled and the MulAmt in simm12. - if (Subtarget.hasVendorXqciac() && isInt<12>(MulAmt)) + if (Subtarget.hasVendorXqciac() && isInt<12>(CNode->getSExtValue())) return SDValue(); const bool HasShlAdd = Subtarget.hasStdExtZba() || |