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| author | Pengcheng Wang <wangpengcheng.pp@bytedance.com> | 2024-11-28 15:01:49 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-28 15:01:49 +0800 |
| commit | d36a4c07156de01b05ea41d5876c671de64e99c6 (patch) | |
| tree | 802e7202244aee03feb78eda2277eda1640b84c2 /llvm/lib | |
| parent | f3cf24fcc46ab1b9612d7dcb55ec5f18ea2dc62f (diff) | |
| download | llvm-d36a4c07156de01b05ea41d5876c671de64e99c6.zip llvm-d36a4c07156de01b05ea41d5876c671de64e99c6.tar.gz llvm-d36a4c07156de01b05ea41d5876c671de64e99c6.tar.bz2 | |
[RISCV] Rename some Feature* to Tune* (#117966)
These features should be tune features.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVProcessors.td | 22 |
2 files changed, 13 insertions, 13 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 7f0bdf3..3fb76c7 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1388,10 +1388,10 @@ def FeatureUnalignedVectorMem "true", "Has reasonably performant unaligned vector " "loads and stores">; -def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", +def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; -def FeaturePredictableSelectIsExpensive +def TunePredictableSelectIsExpensive : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true", "Prefer likely predicted branches over selects">; diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 145af4e..471f051 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -95,7 +95,7 @@ def ROCKET : RISCVTuneProcessorModel<"rocket", defvar SiFive7TuneFeatures = [TuneSiFive7, TuneNoDefaultUnroll, TuneShortForwardBranchOpt, - FeaturePostRAScheduler]; + TunePostRAScheduler]; def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series", SiFive7Model, SiFive7TuneFeatures>; @@ -251,7 +251,7 @@ defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll, TuneConditionalCompressedMoveFusion, TuneLUIADDIFusion, TuneAUIPCADDIFusion, - FeaturePostRAScheduler]; + TunePostRAScheduler]; def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, !listconcat(RVA22U64Features, @@ -300,7 +300,7 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, TuneAUIPCADDIFusion, TuneNoSinkSplatOperands, TuneVXRMPipelineFlush, - FeaturePostRAScheduler]>; + TunePostRAScheduler]>; def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", SyntacoreSCR1Model, @@ -329,7 +329,7 @@ def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32", FeatureStdExtZifencei, FeatureStdExtM, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64", SyntacoreSCR3RV64Model, @@ -340,7 +340,7 @@ def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64", FeatureStdExtM, FeatureStdExtA, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32", SyntacoreSCR4RV32Model, @@ -352,7 +352,7 @@ def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64", SyntacoreSCR4RV64Model, @@ -365,7 +365,7 @@ def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32", SyntacoreSCR5RV32Model, @@ -378,7 +378,7 @@ def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64", SyntacoreSCR5RV64Model, @@ -391,7 +391,7 @@ def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", SyntacoreSCR7Model, @@ -410,7 +410,7 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZbc, FeatureStdExtZbs, FeatureStdExtZkn], - [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + [TuneNoDefaultUnroll, TunePostRAScheduler]>; def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", NoSchedModel, @@ -432,7 +432,7 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", FeatureUnalignedVectorMem]), [TuneNoDefaultUnroll, TuneOptimizedZeroStrideLoad, - FeaturePostRAScheduler]>; + TunePostRAScheduler]>; def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", NoSchedModel, |