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| author | Craig Topper <craig.topper@sifive.com> | 2021-06-08 09:14:26 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-06-08 09:22:40 -0700 |
| commit | c57bce9cc5facbdde52c24fe64fa4f6bf23a8449 (patch) | |
| tree | 45d9e3a617a1fcf69adeb7a7d27db36ce9173338 /llvm/lib | |
| parent | 928a197d26ffd035bc4279ba533f169190a03574 (diff) | |
| download | llvm-c57bce9cc5facbdde52c24fe64fa4f6bf23a8449.zip llvm-c57bce9cc5facbdde52c24fe64fa4f6bf23a8449.tar.gz llvm-c57bce9cc5facbdde52c24fe64fa4f6bf23a8449.tar.bz2 | |
[RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions.
In 0.9 these were defined to leave elements other than 0 in the
destination unmodified. They were changed to use the tail policy
in 0.10. I missed that update.
I assume no one has noticed because in order cores treat tail
agnostic the same as tail undisturbed. I believe Spike and QEMU do
the same.
Reviewed By: arcbbb, frasercrmck
Differential Revision: https://reviews.llvm.org/D103736
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 74bd0d4..9a1c322 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -1978,7 +1978,6 @@ multiclass VPseudoBinaryM_VX_VI { multiclass VPseudoReductionV_VS { foreach m = MxList.m in { - let ForceTailAgnostic = true in defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>; } } @@ -3809,7 +3808,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { (ins m.vrclass:$rs2, ixlenimm:$sew), []>, RISCVVPseudo; let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, - ForceTailAgnostic = true, Constraints = "$rd = $rs1" in + Constraints = "$rd = $rs1" in def PseudoVMV_S_X # "_" # m.MX: Pseudo<(outs m.vrclass:$rd), (ins m.vrclass:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew), @@ -3835,7 +3834,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { ixlenimm:$sew), []>, RISCVVPseudo; let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, - ForceTailAgnostic = true, Constraints = "$rd = $rs1" in + Constraints = "$rd = $rs1" in def "PseudoVFMV_S_" # f.FX # "_" # m.MX : Pseudo<(outs m.vrclass:$rd), (ins m.vrclass:$rs1, f.fprclass:$rs2, |